Parallel FET Solid State Relay Utilizing Commutation FETs
a relay circuit and parallel fet technology, applied in the direction of electronic switching, pulse technique, electric apparatus, etc., to achieve the effect of less resistan
Active Publication Date: 2015-01-15
ASTRONICS ADVANCED ELECTRONICS SYST
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- Description
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- Application Information
AI Technical Summary
Benefits of technology
[0005]The disclosed relay circuit has several advantages. It has a lower overall resistance during solid state operation than would a comparative circuit in which each FET is sized to handle the commutation load. Also, the aforementioned operation of the gates causes the secondary FETs to be protected from possible damage, such as by overheating, that may otherwise occur from the secondary FETs bearing the commutation stress during activation or deactivation of the circuit.
Problems solved by technology
Also, the aforementioned operation of the gates causes the secondary FETs to be protected from possible damage, such as by overheating, that may otherwise occur from the secondary FETs bearing the commutation stress during activation or deactivation of the circuit.
Method used
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Embodiment Construction
[0017]FIG. 1 is a diagram of a basic embodiment. Power source 101 provides power to FET unit 102. Commutation FET 103 is connected in parallel with secondary FET 104 to form a solid state relay circuit. Secondary FET 104 has a lower resistance and is smaller than FET 103. The circuit includes first gate drive 105 and second gate drive 106. First gate drive 105 and second gate drive 106 together ensure that, when commutation FET 103 and secondary FET 104 are activated, commutation FET 103 is driven on before secondary FET 104. First gate drive 105 and second gate drive 106 also ensure that, when commutation FET 103 and secondary FET 104 are deactivated, commutation FET 103 is driven off only after secondary FET 104.
[0018]FIG. 2 is a schematic of an embodiment having two FETs. Driver 201 provides power to the relay circuit and receives on / off commands along line 202. Commutation FET 203 and secondary FET 204 are connected in parallel to driver 201 and first terminal 205 and second ter...
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A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.
Description
FIELD OF THE DISCLOSURE[0001]The subject matter of the present disclosure generally relates to solid state relay circuits, and more particularly relates to solid state relay circuits utilizing parallel field effect transistors.BACKGROUND OF THE DISCLOSURE[0002]Field effect transistors (FETs) are transistors in which the voltage at a gate is used to create a field that either facilitates or prevents conduction between a source terminal and a drain terminal. Multiple FETs connected in parallel have previously been utilized in electrical switch devices to reduce the overall resistance of such devices. However, such designs had the disadvantage that one of the FETs connected in parallel would be the first to experience the entire commutation stress of the switch upon activation and likewise one of the FETs would experience the entire commutation stress of the switch upon deactivation. Therefore, each FET had to be sufficiently large to handle the entire commutation stress and the reduct...
Claims
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IPC IPC(8): H03K17/687
CPCH03K17/687H03K17/122H03K2217/0036
Inventor POTTER, FREDERICK J.MORAVEC, RAYMOND
Owner ASTRONICS ADVANCED ELECTRONICS SYST