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Split-level history buffer in a computer processing unit

a history buffer and split-level technology, applied in computing, concurrent instruction execution, instruments, etc., can solve problems such as affecting cpu performan

Inactive Publication Date: 2016-12-22
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The split-level history buffer system enhances CPU performance by effectively managing architected register data, increasing the number of history buffer entries, and reducing the required circuit area, leading to improved data processing efficiency.

Problems solved by technology

In some instances, a limited number of entries in the HB may reach a memory capacity and impact CPU performance.

Method used

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  • Split-level history buffer in a computer processing unit
  • Split-level history buffer in a computer processing unit
  • Split-level history buffer in a computer processing unit

Examples

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Embodiment Construction

[0010]Embodiments of the present invention provide efficient and cost-effective systems and methods for managing architected register data within computing processing units. Embodiments of the present invention can help increase a total number of history buffer entries in a circuit containing architected register data. Furthermore, embodiments of the present invention may be used to reduce a circuit area required for the total number of history buffer entries.

[0011]FIG. 1 is a functional block diagram of computing environment 100, in accordance with an embodiment of the present invention. In an embodiment, computing environment 100 includes computer system 101. Furthermore, computer system 101 includes instruction fetch unit 102, register file 104, execution unit 106, L1 history buffer (HB) 118, and L2 HB 120. It should be understood that, additional components may be implemented by computer system 101 that perform operations (e.g., arithmetic, logical, control, input / output (I / O), ...

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Abstract

A split level history buffer in a central processing unit is provided. A history buffer is split into a first portion and a second portion. An instruction fetch unit fetches and tags instructions with unique tags. A register file stores tagged instructions. An execution unit generates results for tagged instructions. A first instruction is fetched, tagged, and stored in an entry of the register file. A second instruction is fetched and tagged, and then evicts the first instruction from the register file, such that the second instruction is stored in the entry of the register file. Subsequently, the first instruction is stored in an entry in the first portion of the history buffer. After a result for the first instruction is generated, the first instruction is moved from the first portion of the history buffer to the second portion of the history buffer.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates generally to the field of data processing systems, and more particularly to history buffers in a central processing unit.[0002]Central processing units (CPUs) may implement multi-threaded core technologies that involve one or more execution lanes. Each execution lane utilizes a register file (RF) and history buffer (HB) that contains architected register data. Instructions are tagged by the order in which they were fetched. Once the instructions are fetched and tagged, the instructions are then executed to generate results, which also are tagged. The RF may contain results from the most recently executed instructions (i.e., newer register data) and the HB may contain results from previously executed instructions (i.e., older register data). Furthermore, the older register data is displaced by newer register data from one or more entries in the RF to one or more entries of the HB. In some instances, a limited number of en...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/38
CPCG06F9/3802G06F9/3863G06F9/3814G06F9/3856G06F9/38585G06F9/3861G06F9/30145G06F9/3806G06F9/30098
Inventor LE, HUNG Q.NGUYEN, DUNG Q.TERRY, DAVID R.
Owner INT BUSINESS MASCH CORP