Semiconductor memory device for performing a post package repair operation and operating method thereof

Abstract

A semiconductor memory device includes a fuse array circuit including a row fuse region and a column fuse region, and suitable for outputting fuse information from row fuse sets and from column fuse sets and outputting programmed row and column addresses as row and column fail data, during a boot-up operation; a fuse array control circuit suitable for storing a fail address based on a fail cell information during a repair operation, searching unused fuse sets to from the row fuse region and the column fuse region based on the fuse information during the boot-up operation, and controlling the fail address to be programmed in the unused fuse sets during a rupture operation; and a row and column redundancy circuit suitable for performing a row or column redundancy operation in correspondence to the row and column fail data.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2016-0090840 filed on Jul. 18, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.TECHNICAL FIELD[0002]Exemplary embodiments relate to a semiconductor design technology, and more particularly, to a semiconductor memory device capable of performing a post package repair operation and an operating method thereof.DISCUSSION OF THE RELATED ART[0003]In general, in a semiconductor memory device such as a dynamic random access memory (DRAM), after design and fabrication, the pass or fail of a chip is determined through a test at a wafer level (hereinafter, referred to as a ‘wafer test’) and a test after packaging (hereinafter, referred to as a ‘post package test’).[0004]Typically, when a few or even just one among a number of memory cells which are tested in a semiconductor memory devi...

AI Technical Summary

Benefits of technology

Enables significant improvement in yield by supporting both row and column repair operations, effectively addressing inefficiencies in existing post package repair methods.

Problems solved by technology

Typically, when a few or even just one among a number of memory cells which are tested in a semiconductor memory device fail, the semiconductor memory device cannot perform properly and is considered a defective product which should be discarded.

Discarding a semiconductor memory device as a defective product in the case where only a small number of memory cells fail, is inefficient and decreases the yield.

Therefore, in the case where a column-oriented fail occurs, repair is impossible and thus the yield may decrease.

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