Semiconductor package, interposer and semiconductor process for manufacturing the same

Abstract

A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at least one first columnar portion and at least one first conductive layer. The first columnar portion protrudes from a bottom surface of the first main body. The first conductive layer is disposed on a side surface of the first columnar portion. The second semiconductor device includes a second main body, at least one second columnar portion and at least one second conductive layer. The second columnar portion protrudes from a top surface of the second main body. The second conductive layer is disposed on a side surface of the second columnar portion. The first conductive layer is electrically coupled to the second conductive layer.

Description

BACKGROUND1. Field of the Disclosure[0001]The present disclosure relates to a semiconductor package, an interposer and a semiconductor process for manufacturing the same, and more particularly to a semiconductor package, an interposer capable of providing substantially tenon-type interconnections between a plurality of semiconductor devices, and a semiconductor process for manufacturing the same.2. Description of the Related Art[0002]A conventional semiconductor package may include a semiconductor chip and a substrate or other semiconductor device such as an interposer. The substrate may include a redistribution layer (RDL) and bump pads. The semiconductor chip may include pillars bonded to the bump pads in a chip bonding area of the substrate. The bonding between the pillars and the bump pads may suffer from incomplete joint connection or even bump crack (e.g., intermetallic compound (IMC) crack) due to low tolerance to lateral stress. In particular, in the conventional semiconduct...

AI Technical Summary

Benefits of technology

The patent text describes a semiconductor package and an interposer that have multiple columnar portions and conductive layers for electrical coupling. The main technical effects of the patent text are that it provides a way to increase the density of semiconductor devices by using space on the sides of columnar portions and that it simplifies the manufacturing process by providing a pre-formed main body with conductive layers already applied.

Problems solved by technology

The bonding between the pillars and the bump pads may suffer from incomplete joint connection or even bump crack (e.g., intermetallic compound (IMC) crack) due to low tolerance to lateral stress.

However, the capability against warpage of conventional bonding between the pillars and the bump pads cannot be significantly improved because the conventional bonding configuration does not provide sufficient lateral stress tolerance.

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