Simultaneous write, read, and command-address-control calibration of an interface within a circuit

Abstract

A calibration controller tests an electronic circuit to identify an initial read check with a read delay, an initial write check with a write delay, and an initial command, address, control (CAC) check with a CAC delay indicated as passing. Responsive to the initial read check, the initial write check, and the initial CAC check indicated as passing, for each setting of the read delay, the write delay, and the CAC delay, the calibration controller iteratively performs concurrently, a write test with the write delay, a read test with the read delay, and a CAC test with the CAC delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until one or more of a read edge, a write edge, and a CAC edge are detected.

Description

BACKGROUND1. Technical Field[0001]This invention relates in general to a memory system calibration and more particularly to simultaneous write, read, and command-address-control (CAC) calibration of an interface within a circuit.2. Description of the Related Art[0002]Computing systems generally include one or more circuits with one or more memory or storage devices connected to one or more processors via one or more controllers. Timing variations, frequency, temperature, aging, and other conditions impact data transfer rates to and from memory or other storage, which impacts computer system performance, and reliability. As operating frequencies increase, the valid window for read signals, write signals, and CAC signals to be latched within decreases. Given the high clock rates and fast edge speed used in many computer systems, timing variations and timing skews from one system implementation to another are challenging and time consuming to calibrate, especially for systems with larg...

AI Technical Summary

Benefits of technology

The patent describes a method and computer system for testing an electronic circuit to identify its initial read, write, and CAC checks, which all pass. The method involves performing a series of tests while adjusting the timing of the read and write delays and the CAC check until certain edges are detected. The technical effect of the patent is to provide a reliable and efficient way to test the initial performance of electronic circuits.

Problems solved by technology

Timing variations, frequency, temperature, aging, and other conditions impact data transfer rates to and from memory or other storage, which impacts computer system performance, and reliability.

Given the high clock rates and fast edge speed used in many computer systems, timing variations and timing skews from one system implementation to another are challenging and time consuming to calibrate, especially for systems with larger amounts of memory and a greater overall width of the memory bus.

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