Fractional divider for modulated phase-lock loop circuits

Abstract

Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to oscillator circuits. More particularly, embodiments of the present invention relate to fractional dividers for modulated phase-lock loop circuits.BACKGROUND OF THE INVENTION[0002]Many types of electronic applications can include clock circuits, or the like, which can rely on a stable frequency reference. Some such applications use a crystal oscillator, or other suitably accurate oscillator, to generate a reference frequency. The reference frequency can then be fed into a phase-locked loop (PLL), which can output some desired multiple of the reference frequency. Typically, the PLL has a feedback loop that includes a divider, and the output of the divider is fed back as an input to the PLL, along with the reference frequency. In that way, a dividing value associated with the divider can be used effectively to control the multiple relationship between the PLL output frequency and the reference frequency.[0003]In som...

AI Technical Summary

Benefits of technology

The patent text describes circuits, devices, and methods for implementing fractional dividers in modulated phase-lock loop circuits. The system uses a fractional shifting modulator to generate a shifted fractional component value, which is then added to a base dividing value to generate a corrected dividing value. A feedback signal is then generated by sequentially dividing the clock output signal by the corrected dividing value. The technical effect of the patent text is to provide a more efficient and accurate way to implement fractional dividers in phase-lock loop circuits.

Problems solved by technology

In such applications, conventional approaches to generating fractional dividing values in a PLL tend to produce undesirable results.

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