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Memory device supporting interleaved operations and memory system including the same

Pending Publication Date: 2022-04-28
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present patent is related to a memory device and system that supports an interleaving operation mode. The technical effects of this patent include improved data processing speed and reliability of the memory system. The memory device includes a control logic circuit and a voltage generation circuit that work together to efficiently perform interleaving operations. The system includes a memory controller and a memory device, which supports interleaving operations. The memory device includes a specific operation method for interleaving operations. The patent also describes various embodiments and variations of the memory system and their features.

Problems solved by technology

A volatile memory device is a device that stores data only when power is supplied and loses the stored data when the power supply is cut off.

Method used

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  • Memory device supporting interleaved operations and memory system including the same
  • Memory device supporting interleaved operations and memory system including the same
  • Memory device supporting interleaved operations and memory system including the same

Examples

Experimental program
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Embodiment Construction

[0020]Various embodiments of the present disclosure are described below with reference to the accompanying drawings. Elements and features of the disclosure, however, may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0021]In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,”“example embodiments,”“an embodiment,”“another embodiment,”“some embodiments,”“various embodiments,”“other embodiments,”“alternative embodiments,” and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

[0022]In this disclosure, the terms “comprise,”“comprising,”“include,” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the stated ele...

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PUM

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Abstract

A memory system includes a first memory die including multiple planes each including a plurality of memory cells and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die. After transferring an erase command to a plane among the multiple planes, the controller transfers a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a continuation-in-part application of U.S. patent application Ser. No. 17 / 244,060, filed on Apr. 29, 2021, which claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0139606 filed on Oct. 26, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.BACKGROUND1. Technical Field[0002]The present disclosure relates to an electronic device, and more particularly, to a memory device and a memory system including the same supporting an interleaving operation mode.2. Related Art[0003]A memory system is a device that stores data under the control of a host device such as a computer or a smartphone. The memory system may include a memory device in which data is stored and a memory controller controlling the memory device. The memory device is divided into a volatile memory device and a nonvolatile memory device.[0004]A volatile memory dev...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C16/14G11C16/26G11C16/30G11C7/10
CPCG11C16/14G11C7/1039G11C16/30G11C16/26G11C16/08G11C16/32G11C16/10G11C2211/5648G11C11/5628G11C5/02G11C7/1042
Inventor CHOI, WON JAECHOI, JEA WON
Owner SK HYNIX INC