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Queueing architecture and load balancing for parallel packet processing in communication networks
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a technology of parallel packet processing and queueing, applied in the direction of data switching network, data switching by path configuration, digital transmission, etc., can solve the problems of load balancing and increasing the complexity of the processing per pack
Active Publication Date: 2008-01-08
CISCO TECH INC
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[0012]In one embodiment of the present invention, the parallel packet processing system has a queuing architecture that is referred to as a per-Cell-Contiguous-Queuing architecture or CCQ architecture because of the way it distributes the packet to the processor queues. First, the first or start or starting queue into which to enqueue the first or head cell of
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Additionally, the processing per packet is becoming more complex.
An important issue in every parallel and distributed processing architecture is that of load balancing.
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case i
[0040] Let the packet have size p=hC+r, where h<K and r<C, that is, the no processor queue will receive more than C bits of this packet. Consider the following two sub-cases:
[0041]Case I.A: Suppose B(T) is non-empty and without any loss of generality assume that A(T)={1, 2, 3, . . . , m} and B(T)={m+1, m+2, . . . , K} for some m=1, 2, 3, . . . K−1. Note that according to the previous definitions, 0<=L(1;T)−Lmin(T)<C, but the queue preceding 1 (modulo K, that is, queue K) has C<=L(K;T)−Lmin(T)<2C. Hence, the load balancing / round robin scheme will place the first cell of the new packet in queue 1.
[0042]Then, at time t=aC+b
L(k;t)=L(k;t)+C, for k=1, 2, . . . , a
L(k;t)=L(k;t)+b, for k=a+1
L(k;t)=L(k;t), for k=a+2, a+3, . . . K.
Consider now the evolution of the queue loads as the packet cells are placed in the processor queues according to the load balancing / round robin scheme. As a matter of fact, consider the most general case, where a>m, so that packet bits will be...
case ii
[0045] If p=zKC+kC+r, where k
[0046]Based on the above we see that the backlog in any of the processor queues does not exceed 2C under the load balancing / round robin celldistribution method. Hence, with a queue size of 2C bits on every processor, the load balancing / round robin cell distribution method does not cause a packet to be dropped under normal operation of the system.
[0047]From the above discussion, it is clear that for packet sizes that are smaller than C bits, the PQ and CCQ queuing architectures operate quite similarly. However, CCQ provides significant benefits compared with PQ when packet sizes are larger than C bits. To see why CCQ provides benefits over PQ, consider the limiting case where C=1, that is, each packet is divi...
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Abstract
A parallel packet processing queueing architecture and method are described. A packet is divided up into cells. A first or start processor queue is selected for the first cell. The following cells of the packet are then placed in the queues in a predetermined order. An example of a predetermined order is placing the cells in consecutive processor queues modulo (the number of processor queues) after the start processor. Such a predetermined order is illustrated in the context of a per Cell Contiguous Queueing (CCQ) architecture. The architecture provides benefits of alleviating the pre-processing and post-processing buffering burdens and decreasing the amount of information required for reassembly of the packet.
Description
CROSS-RELATED APPLICATION[0001]This application claims priority under 35 U.S.C. § 119(e) to U.S. provisional patent application, “Queuing Architecture and Load Balancing Method for Parallel Packet Processing in Communication Networks,” having a Ser. No. 60 / 329,425 and a filing date Oct. 13, 2001. The subject matter of the foregoing is incorporated herein by reference in its entirety.BACKGROUNDField of the Invention[0002]This invention relates to the field of parallel packet processing in communication networks.[0003]As communication networks scale up in terms of speed and capacity, packets being switched and routed through network nodes need to be processed at increasingly higher speeds, matching those of the communication network links. Additionally, the processing per packet is becoming more complex. The processing involves not only determining the destination of the packet but the processing of security parameters of the packet. As a result, parallel packet processing architectur...
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