Reduced-edge radiation-tolerant non-volatile transistor memory cells

Abstract

An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to non-volatile memory cells. More particularly, the present invention relates to reduced-edge, radiation-tolerant, non-volatile transistor cells for memories or programmable logic devices.[0003]2. The Prior Art[0004]Reduced edge transistors such as so-called “H-gates” used in regular logic have been employed to increase radiation tolerance of such circuits. A special case of reduced edge transistors is so-called “edgeless” transistors. Edgeless or circle-gate transistors have also been used in logic and other peripheral circuits and charge pumps to eliminate increased leakage due to exposure to ionizing radiation. Although such radiation-hardening techniques have been applied to standard single-polysilicon-gate devices, they have not been applied to programmable non-volatile memories.[0005]Antifuse-based radiation tolerant products available from Actel Corp. of Mountain View, Calif. includ...

AI Technical Summary

Problems solved by technology

Although such radiation-hardening techniques have been applied to standard single-polysilicon-gate devices, they have not been applied to programmable non-volatile memories.

A major challenge using prior art non-volatile transistors in a radiation environment is known as Total Dose.

Positive ions tend to become lodged in the silicon dioxide regions of the semiconductor—and are a particular problem in the Shallow Trench Isolation (STI) silicon dioxide areas used to electrically isolate transistors in modern deep-submicron processes.

This effectively lowers the threshold voltage of the transistor locally near the edges of the transistor where the STI is located and can cause current leakage along the edge of the transistor.

The leakage can cause undesirable power consumption, may interfere with re-programming the cell, and, in extreme cases, may cause the off state of the transistor to read as on.

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