Dummy gate technology to avoid shorting circuit

Abstract

Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Description

BACKGROUND OF THE INVENTION[0001]Field of the Invention[0002]Embodiments of the invention relate to static random access memory (SRAM) to be used for storage on integrated circuit devices, and more particularly to advanced SRAM cells using one or more fin field-effect transistor (FinFET) structures. The present invention also relates to the design layout and manufacturing process for fabricating SRAM cells with such fin field-effect transistor structures.[0003]Description of the Related Art[0004]Modern digital data processors generally use several different types of memory devices to answer different performance and functional requirements. Dynamic memories generally store data as charge in a capacitor to allow much faster access, and can be selectively addressed for storing smaller amounts of data each time. However, dynamic memories must be periodically refreshed to compensate for charge that may leak from its capacitors, leading to undesirable longer access time.[0005]Static memo...

AI Technical Summary

Benefits of technology

The invention provides a method for designing and fabricating a semiconductor memory device that avoids electrical shorting through a nearby dummy gate. The method includes sectionalizing the dummy gate line at a location between the metal contacts of a nearby cell to prevent shorting with nearby metal contacts of a neighboring cell. The method also includes patterning the gate layer according to a gate slot pattern and a gate line pattern to form the first and second gate lines, and the first and second dummy gate lines in the active and dummy edge cells, respectively. The distance between the metal contacts and the dummy gate lines is set to prevent shorting. The invention provides a semiconductor memory device that has improved performance and reliability.

Problems solved by technology

It was found that in the neighboring bit cell, various metal contacts, including bit line metal contacts, VSS contacts, VCC contacts, etc., which are positioned next to a dummy gate line of the edge cell have the risk of shorting through the dummy gate line of the edge cell,

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