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Information processing apparatus and memory control method

a technology of information processing apparatus and memory control, applied in the field of information processing apparatus, can solve the problems of low process speed, easy occurrence of bank conflicts, and inability to process accesses simultaneously, and achieve the effect of reducing bank conflicts

Active Publication Date: 2018-04-17
CANON KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a way to reduce conflicts between banks by using statistical information to allocate memory access. The technical effect is to improve the efficiency and reliability of computer systems.

Problems solved by technology

Hence, when accesses occur simultaneously from a plurality of processor elements to a plurality of portions belonging to the same bank, the accesses cannot be processed simultaneously, and the process speed lowers.
In general, bank conflict readily occurs in a parallel processing apparatus or system which has a relatively high throughput and performs access to a shared memory using a plurality of processor elements in parallel.
If a number of image processes are parallelly performed for the recognition process, bank conflict may occur, resulting in a decrease in the process speed.
In some cases, however, data cannot apply to any pattern.
In this case, the above technique produces only a poor effect of reducing bank conflict.

Method used

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  • Information processing apparatus and memory control method
  • Information processing apparatus and memory control method

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Experimental program
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first embodiment

[0028]Memory access control in an information processing apparatus that performs a process of recognizing the position and orientation of an object by an image process (to be referred to as “recognition process for object position and orientation” hereinafter) will be described below. The recognition process for object position and orientation is executed by, for example, a robot system which executes a task such as picking a part on, for example, a production line of a factory to recognize the positions and orientations of stacked parts by an image process.

[0029]The recognition process for object position and orientation and prerequisites therefor will be described first.

[0030][Recognition Process for Object Position and Orientation]

[0031]Image process target data such as an image obtained by capturing parts will be defined as “image data,” image data extracted from image data will be defined as “partial image data,” and data such as parameters necessary for an image process other ...

second embodiment

[0056]The second embodiment of the present invention will be described below. In the second embodiment, a case will be explained in which a process of picking a part is repeated after a recognition process for object position and orientation for parts is performed. Note that only points different from the processes performed by the information processing apparatus according to the first embodiment will be described here, and the rest is the same as in the first embodiment.

[0057][Picking Process]

[0058]FIG. 5 is a flowchart showing a part picking process performed by an information processing apparatus according to the second embodiment.

[0059]First, a statistical information obtaining process is performed as in step S201 of FIG. 2 (S501). More specifically, a host processor 15 obtains statistical information for a recognition process for object position and orientation (S504) of the subsequent stage. The statistical information obtained here represents a memory access frequency distri...

third embodiment

[0082]The third embodiment of the present invention will be described below. In the third embodiment, an example will be explained in which a specific target object moving on an image is recognized and tracked in a moving image data process or the like. Note that only points different from the processes performed by the information processing apparatuses according to the first and second embodiments will be described here, and the rest is the same as in the first and second embodiments. Note that the target object to be tracked is assumed to only translate on a screen for a descriptive convenience. In addition, the number of target objects is limited to one.

[0083][Tracking Process]

[0084]FIG. 8 is a flowchart showing a tracking process performed by an information processing apparatus according to the third embodiment.

[0085]First, statistical information (memory access frequency distribution) is obtained as in step S201 of FIG. 2 (S801).

[0086]Next, a host processor 15 performs a bank ...

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Abstract

An information processing apparatus comprises a plurality of processor elements, and a memory having a plurality of banks. Statistical information representing an access frequency distribution to each memory area of the memory by the plurality of processor elements is obtained. An allocation process of allocating the banks to the memory areas is performed based on the statistical information.

Description

BACKGROUND OF THE INVENTION[0001]Field of the Invention[0002]The present invention relates to an information processing apparatus comprising a plurality of processor elements and a memory having a plurality of banks, and memory control thereof.[0003]Description of the Related Art[0004]In an information processing apparatus using a plurality of processor elements and a memory having a plurality of banks, when the plurality of processor elements access the memory, only one portion of each bank is accessible at once. Hence, when accesses occur simultaneously from a plurality of processor elements to a plurality of portions belonging to the same bank, the accesses cannot be processed simultaneously, and the process speed lowers. This situation is called “bank conflict.”[0005]In general, bank conflict readily occurs in a parallel processing apparatus or system which has a relatively high throughput and performs access to a shared memory using a plurality of processor elements in parallel...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F12/06
CPCG06F12/0607G06F12/0623
Inventor HONJO, TOMOYAYAMAMOTO, TAKAHISA
Owner CANON KK