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System management memory for system management interrupt handler independent of BIOS and operating system

a technology of interrupt handler and system management memory, applied in the field of computer systems, can solve the problems of large amount of time and effort, neither of these alternatives is desirable,

Inactive Publication Date: 2005-12-27
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention pertains to a system management interrupt (SMI) in computer systems. More specifically, it introduces a memory controller that integrates a system management memory region, which allows chipset or other system component manufacturers to distribute proprietary SMI routines without the need to involve BIOS or operating system vendors. This integration eliminates the need for negotiations with multiple parties and reduces the time and effort required for such negotiations. The technical effect of this invention is to provide a more efficient and flexible way of managing SMI events in computer systems.

Problems solved by technology

Neither of these alternatives is desirable, in large part to the large amount of time and effort required to perform the negotiations and to implement the chipset manufacture's requests.

Method used

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  • System management memory for system management interrupt handler independent of BIOS and operating system
  • System management memory for system management interrupt handler independent of BIOS and operating system
  • System management memory for system management interrupt handler independent of BIOS and operating system

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Embodiment Construction

[0010]An embodiment of a memory controller with an integrated system management memory region will be described. The memory controller receives an SML acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed. The integrated system management memory region allows chipset or other system component manufacturers to distribute proprietary SMI routines without the need to involve BIOS or operating system vendors. The proprietary SMI routines may be uti...

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PUM

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Abstract

A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.

Description

FIELD OF THE INVENTION[0001]The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of integrating a system management memory into a memory controller for a system management interrupt handler that is independent of both BIOS and operating system.BACKGROUND OF THE INVENTION[0002]A large majority of today's personal computer systems implement a system management interrupt (SMI). An SMI signal is asserted to a processor to alert the processor that an SMI event has occurred. The SMI signal is typically asserted to the processor by a system logic device that includes a memory controller. The system logic device may assert the SMI signal for any of a large number of possible reasons. For example, the SMI signal may be asserted if a system resource seeks access to a certain range of memory or to a particular input / output address. These memory and input / output addresses can be programmable via a set of registers that typicall...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F9/48
CPCG06F9/4812G06F9/445
Inventor MARTWICK, ANDREW W.
Owner INTEL CORP