Unlock instant, AI-driven research and patent intelligence for your innovation.

Process and device for optically erasing charge buildup during fabrication of an integrated circuit

An integrated circuit, charge accumulation technology, applied in circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as difficult to penetrate IC structures

Inactive Publication Date: 2007-09-05
AXCELIS TECHNOLOGIES
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The net result is that it is more difficult for light of a given narrowband wavelength to penetrate the IC structure and erase the charge build-up generated during the manufacturing process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Process and device for optically erasing charge buildup during fabrication of an integrated circuit
  • Process and device for optically erasing charge buildup during fabrication of an integrated circuit
  • Process and device for optically erasing charge buildup during fabrication of an integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0041] In this example, the wafer was exposed to a broadband radiation pattern generated by a FUSION PS3 exposure tool. The exposure tool was equipped with an HL bulb and produced the spectral pattern shown in FIG. 4 . The FUSION PS3 Exposure Tool is a commercially available exposure tool manufactured by Axcelis Technologies, Inc. of Rockville, MD. Each wafer includes a plurality of dies containing non-volatile memory (NVM or flash memory) structures that are preprogrammed to a state of charge using electrical probes. The non-volatile memory structure includes a conductive gate disposed over a floating gate electrode based on a 250nm design rule. The electrical power supplied to the magnetron in the microwave circuit is 4500 watts (W), and the transfer efficiency of the microwave circuit to the bulb is reduced to about 67% (ie about 3000 watts for the bulb).

[0042] The exposure time was varied for different wafer sets, and the charge on the gate was plotted as a function o...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A process for optically reducing charge build-up in an integrated circuit includes exposing the integrated circuit or portions thereof to a broadband radiation source. The process effectively reduces charge buildup that occurs in the manufacture of integrated circuits.

Description

technical field [0001] The present disclosure relates generally to methods and apparatus for fabricating integrated circuits, and more particularly, to methods and apparatus for optically removing or reducing charge buildup generated during fabrication of integrated circuit devices. Background technique [0002] Various integrated circuits employing non-volatile memory (NVM) arrays have been proposed or used in the industry. Non-volatile memory arrays are usually based on floating gate technology. This technique refers to transferring charge through an oxide or dielectric layer to a conductive floating gate, where it is then stored or removed. An example of a non-volatile memory array device using floating gate technology is an Erasable Programmable Read Only Memory ("EPROM") device, which can be read, erased, and written (ie, programmed). EPROMs typically use floating gate field effect transistors that have a binary state depending on the presence or absence of charge on ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8247H01L21/02H10B69/00H01L21/268H01L21/28H01L21/336
CPCH01L21/268H01L29/66825H01L21/28176H01L29/66477
Inventor A·亚诺斯I·贝里A·辛诺特K·斯图尔特
Owner AXCELIS TECHNOLOGIES