Check patentability & draft patents in minutes with Patsnap Eureka AI!

Forming polysilicon structures

A technology of polysilicon and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as etching deviation

Inactive Publication Date: 2008-01-02
INTEL CORP
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, etching doped polysilicon presents significant challenges
These challenges include known profile issues and differential etch bias issues

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Forming polysilicon structures

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] Referring to FIG. 1, a semiconductor substrate may have a polysilicon material formed on a suitable gate dielectric. The substrate may be, for example, a silicon substrate, and the gate dielectric may be, for example, oxide. Then, as shown in FIG. 1 , the polysilicon material may be patterned to form polysilicon gate material on gate dielectric 12 , all of which are disposed above substrate 10 . Because the polysilicon material is undoped or substantially undoped when etched, it can be easily etched and patterned to define the shape shown in FIG. 1 .

[0014] "Substantially undoped" is used to describe a polysilicon material that is either undoped, or doped at a level substantially lower than that of doped polysilicon that is utilized to form N-type or P-type The doping level of the gate electrode. Typically, these gate electrodes are considered heavily doped and have a doping concentration higher than 1E18 atoms per cubic centimeter.

[0015] Gate material 14 may be...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A doped polysilicon structure may be formed without the need to etch doped polysilicon. The patterned polysilicon may be covered, an opening may be formed in the polysilicon covering, and then the polysilicon may be doped through the opening. As a result, awkward etching of doped polysilicon may be avoided in some cases.

Description

technical field [0001] The present invention generally relates to the formation of polysilicon structures, including the formation of polysilicon gate electrodes. Background technique [0002] Conventionally, polysilicon gate electrodes are formed by depositing polysilicon on a substrate, which may be covered with a suitable gate dielectric. The polysilicon material is then doped using, for example, an ion implantation process. [0003] The polysilicon electrodes must then be defined from the doped polysilicon layer using etching techniques. However, etching doped polysilicon presents significant challenges. These challenges include known profile issues and differential etch bias issues. [0004] Therefore, there is a need to find a way to form polysilicon structures, such as gate electrodes, without having to etch heavily doped polysilicon material. Contents of the invention [0005] According to a first aspect of the present invention there is provided a method of fo...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/8238H01L21/265H01L21/28
CPCH01L21/28035H01L21/26513H01L21/823842
Inventor 桑杰伊·纳塔拉詹凯文·海德里奇伊布拉西姆·班恩
Owner INTEL CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More