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Stack type double-chip packaging structure

A packaging structure, two-chip technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of poor thermal stress reliability, difficult to apply thin structures, etc., to improve reliability and simplify the complex manufacturing process. the effect of reducing the manufacturing cost

Inactive Publication Date: 2008-04-16
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This type of packaging structure needs to grind the chip to a thinner thickness, so it is difficult to directly apply to thin structures, and this packaging structure is an asymmetric structure, and its thermal stress reliability is poor

Method used

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  • Stack type double-chip packaging structure
  • Stack type double-chip packaging structure
  • Stack type double-chip packaging structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0026] Please refer to image 3 , the stacked two-chip package structure of the present invention mainly includes: a first chip 100 , a lead frame, a second chip 200 and a plurality of wires 140 .

[0027] The first chip 100 has an active surface 100a and an opposite non-active surface 100b, wherein the active surface 100a has circuit components and is divided into a central portion and a peripheral portion, and the peripheral portion has a plurality of first pads 120a.

[0028] The lead frame mainly includes: a plurality of pins 400 and a chip supporting seat 300 . Wherein, the above-mentioned chip supporting seat 300 is used for supporting and fixing the chip, and has a first bonding surface 300a and a second bonding surface 300b, and the first bonding surface 300a of the above-mentioned supporting seat 300 is adhered to the above-mentioned chip by solid or liquid glue. In the central part of the active surface 100a of the first chip, the first pad 120a on the active surfac...

Embodiment 2

[0033] Image 6 A structural sectional view of another preferred embodiment of the present invention is shown. The stacked two-chip package structure of the present invention mainly includes: a first chip 100 , a lead frame, a second chip 200 and a plurality of wires 140 . Main structure is all identical with embodiment 1 description.

[0034] However, according to the stacked two-chip package structure of the present invention, in addition to the above structure, an encapsulant 500 can be used to cover the above structure to prevent components from moisture intrusion and mechanical scratches.

[0035] And the lead 400 can extend to the outside of the above-mentioned encapsulant 500 , that is, the outer lead 400 b , and the part wrapped inside the above-mentioned encapsulant 500 is the inner lead 400 a.

Embodiment 3

[0037] Figure 7 and Figure 8A cross-sectional view of a structure according to another preferred embodiment of the present invention is shown. The stacked two-chip package structure of the present invention mainly includes: a first chip 100 , a lead frame, a second chip 200 and a plurality of wires 140 . Main structure is all identical with embodiment 1 description.

[0038] Like the second embodiment, the third embodiment of the present invention can also have encapsulant, and the encapsulation method can also be another type. Except that the non-active surface 100b of the first chip 100 is exposed outside the encapsulant 500 , the other second chips 200 , the pads 120 , the supporting seats 300 , the pins 400 , the wires 140 and the first chip The active surface 100 a of the 100 is covered by the above-mentioned encapsulant 500 .

[0039] In addition, the above pin 400 has two types. One of the types is that the inner lead 400a covered in the above-mentioned encapsula...

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PUM

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Abstract

The invention reveals a stacked double-chip package structure, and its characteristic: using a smaller-area support seat to adhere to a bigger-area action surface of first chip and a non-action surface of second chip, and many peripheral pads and wires of the action surfaces of the two chips are connected with many pins.

Description

technical field [0001] The invention relates to a chip packaging structure, and in particular to a stacked double-chip packaging structure. In this way, the overall thickness of the packaging structure can be reduced. Background technique [0002] With the advancement of semiconductor technology, the execution speed and design complexity of semiconductor chips are increasing day by day. Therefore, the packaging of semiconductors is constantly innovating in order to improve the packaging efficiency. In addition, with the development trend of electronic products towards lightness, thinness, shortness, smallness and multi-functionality, a dual-chip chipset emerges accordingly. Therefore, the stacked package of two chips is constantly evolving in order to reduce the volume of the package. [0003] For clarity, refer to figure 1 , which shows a cross-sectional view of a conventional stacked two-chip package structure. A first chip 1 and a second chip 2 are adhered and fixed ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/04H01L25/16H01L25/18H01L23/48H01L23/28
CPCH01L2224/49175H01L2224/48091H01L2224/73265H01L2224/48247H01L2224/32145H01L2924/181H01L2924/18165H01L2224/05554H01L2224/4826H01L2924/00014H01L2924/00H01L2924/00012
Inventor 蔡振荣林志文
Owner MACRONIX INT CO LTD