Dynamic load allocating method for network processor based on cache and apparatus thereof

A technology of network processor and load distribution, which is applied in the direction of data exchange network, digital transmission system, electrical components, etc. It can solve the problems of out-of-sequence messages and unbalanced loads, so as to avoid message processing bottlenecks, avoid violent oscillations, Efficiently maintain the effect of load balancing

Inactive Publication Date: 2008-04-30
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0004] The technical problem to be solved by the present invention is: aiming at the unbalanced load and out-of-sequence problems caused by each PE that tends to occur under the parallel PE structure of the network processor in the prior art, the present invention provides a A cache-based network processor dynamic load distribution method and device capable of efficiently maintaining load balance and having strong message flow order preservation capabilities

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  • Dynamic load allocating method for network processor based on cache and apparatus thereof
  • Dynamic load allocating method for network processor based on cache and apparatus thereof
  • Dynamic load allocating method for network processor based on cache and apparatus thereof

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Embodiment Construction

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0027] The technical solution of the present invention is to dynamically monitor the load status of each processing unit in the network processor, and adaptively adjust the distribution mode of the wire-speed message flow to each processing unit according to the load status, while adopting a cache structure to maintain the message to each processing unit The allocation status of the unit, and update the allocation status by adjusting the invalidation and replacement timing of cache entries. The distribution method in the present invention is applied to the load distributor inside the network processor chip, such as figure 1 As shown, the IP message sent from the input interface of the network processor is sent to each processing unit for processing after load adjustment in the load distribution unit, and the processed message is sent to the output interface.

[00...

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Abstract

This invention discloses a dynamic load distribution method for network processor based on cache. After a message buffer picks up the source IP address and target IP address, it computes a 16-bit flow identification value with a flow identification hash computation unit and utilizes said value to look for load distribution cache to determine which unit processes said message, if the cache is not shot, it gives the process unit number with the lightest load at present by a load computing unit real time monitoring and processing the load state as the target process unit. A dynamic load distribution device got by this method includes a flow identification hash computing unit, a load distribution cache unit, a computation unit, a message buffer unit and an issue unit.

Description

Technical field [0001] The present invention mainly relates to the field of network processors, and specifically refers to a method and device for dynamic load distribution of a cache-based network processor. Background technique [0002] The network processor is a high-performance "Application Specific Instruction Processor" (ASIP) used for network protocol processing, and is widely used in various network devices, such as router line cards, firewall devices, and network interface cards. The network processor contains multiple processing elements (PE, Processor Element). There are usually two ways to organize processing units: parallel and pipeline structure. The present invention is aimed at the parallel PE structure, such as figure 1 Shown. In the parallel PE structure, each processing unit can independently complete message processing operations without the intervention of other units, but they share the message flow receiving and sending structure. The network processor nee...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/56H04L12/803
Inventor 唐玉华张晓明孙志刚胡晓峰管剑波
Owner NAT UNIV OF DEFENSE TECH
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