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Flat capacitor structure and flat capacitor, grid and resistance forming technique method

A technology of flat plate capacitors and process methods, which is applied in the direction of circuits, electrical components, and electric solid devices, and can solve problems such as hidden dangers of interlayer dielectric thickness uniformity, production loss, and deterioration of resistivity uniformity of low-resistance layer resistance, etc., to achieve improved Film thickness uniformity, uniformity improvement, process simplification effect

Inactive Publication Date: 2008-10-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The biggest problem with such a process is that when etching the interlayer dielectric, the metal layer on the gate and the low-resistance layer will be etched to varying degrees, resulting in deterioration of the in-plane uniformity of the resistivity (ps) of the low-resistance layer. easily cause production loss
In addition, there is a large step between the capacitance area and the diffusion area, which also brings hidden dangers to the thickness uniformity of the interlayer dielectric (PMD) in front of the metal behind.

Method used

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  • Flat capacitor structure and flat capacitor, grid and resistance forming technique method
  • Flat capacitor structure and flat capacitor, grid and resistance forming technique method

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Embodiment Construction

[0010] Such as figure 2 As shown, it is a structural schematic diagram of the plate capacitor 1, the gate 2, the low-resistance layer resistor 3 and the high-resistance layer resistor 4 of the present invention. It uses the injected polysilicon as the lower pole of the capacitor 1, and the interlayer dielectric of the capacitor 1 is prepared before the metal layer PVD of the gate 2, and then PVDs the metal layer of the gate 2 and the upper pole of the capacitor 1 at the same time. When etching, the upper pole of the capacitor 1 is etched together with the metal layer of the gate 2 and the low-resistance layer resistor 3, and then the lower pole of the capacitor 1 and the gate are simultaneously etched using the interlayer dielectric and photoresist as a mask. The polysilicon of electrode 2 / low resistance layer resistance 3 can even be etched into polysilicon with high resistance, and its resistance value can be adjusted by high-energy inversion implantation through the dielec...

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Abstract

This invention discloses one plane capacitor structure and its plate capacitor, grating electrode and resistance form process method, which comprises the following steps: a, depositing multiple silicon chemical phase and injecting phosphor; b, medium chemical phase deposition for growing and to remove capacitor down electrode and high resistance medium subject; c, metal layer splashing; d depositing and growing block oxidation layer phase; e, etching the block oxidation layer and metal layer through light etch glue to form capacitor top electrode and grating electrode and resistance metal layer.

Description

technical field [0001] The invention relates to a process method for forming flat capacitors, gates and resistors. Background technique [0002] Such as figure 1 As shown, it is a schematic diagram of the structure of the existing planar capacitor, gate, low-resistance layer resistance and high-resistance layer resistance. Currently, among products that use polysilicon (Poly) and metal layer (Metal) as the gate (Gate), the planar capacitor It is realized by using the gate layer (Poly+Metal) as the lower plate, depositing the interlayer dielectric by chemical vapor deposition (CVD), and then using physical vapor deposition (PVD) or CVD a layer of Metal as the upper plate. When etching, firstly carve out the upper pole of the capacitor and the interlayer dielectric, and then carve out the lower pole of the capacitor, the Gate and the low-resistance layer resistance. The high-resistance layer resistance requires independent polysilicon (HR polysilicon) growth / implantation and...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/94H01L27/108H01L27/102H01L27/10H01L27/00H01L21/8242H01L21/8222H01L21/82
Inventor 王勤
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP