Pipelined asynchronous instruction processor circuit
An instruction processing and pipeline technology, which is applied in concurrent instruction execution, electrical digital data processing, instruments, etc., and can solve the problem of reversed order of internal instruction results.
Active Publication Date: 2008-11-26
卡莱汉系乐有限公司
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Problems solved by technology
As a result, the results of load instructions may be produced out of order with respect to the results of internal instructions
Method used
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[0023] 1 shows an instruction processing circuit with a plurality of processing stages 10a-e, registers 12a-d, timing circuit 14, write multiplexer 16, register file 17 and instruction memory 18. Processing stages 10a-d are connected in a pipeline by registers 12a-d. With the exception of the first stage 10a, each stage 10b-e has one or more instruction information inputs coupled to the preceding pipeline register 12a-d, and each stage 10a-d except the last stage 10e has a coupled to The instruction information output of the following pipeline registers 12a-d. Both processing stages 10c, d have additional result outputs for outputting the results and accompanying register addresses to the multiplexer 16 . These processing stages 10c,d also have acknowledgment outputs 19a,b coupled to the timing circuit 4 . An acknowledgment output for a stage indicating whether a write from a stage to the register file is required.
[0024] Processing stages are, for example, an instruction...
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A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages (10c, d) are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned (10c, d) requires writing. A write sequencing circuit (144) performs write tests alternately for instruction dependent information in the first and second one of the stages (10c, d). When the write sequencing circuit (144) performs the write test for a particular one of the stages (10c, d), it tests whether the instruction dependent information in the particular one of the stages (10c, d) requires writing of a result. If so, the write sequencing circuit (144), delays transfer of new instruction dependent information through the pipeline (10a-d) to the particular one of the stages (10c,d) until the write port has been committed to writing the result before any results that the write port is subsequently committed to write.
Description
technical field [0001] The invention relates to a data processing circuit with a pipelined asynchronous instruction processor. Background technique [0002] Instruction execution pipelining is a conventional technique in computers that involves the use of an instruction processor that contains multiple stages for performing the various steps of instruction processing. Typical steps include an instruction fetch step, an instruction decode / operand fetch step, an execute (computation) step, and a result writeback step. The stages operate in parallel according to the assembler line principle, whereby an earlier stage performs one step for a first instruction, and a subsequent stage performs a subsequent step for an earlier instruction using a partial result produced by an earlier stage for an earlier instruction . Most modern instruction processors execute with synchronous circuits, that is, circuits in which all stages operate under the control of the same central clock, with...
Claims
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IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/3867G06F9/3824G06F9/3871G06F9/3856
Inventor A·J·宾克M·N·O·德克勒克
Owner 卡莱汉系乐有限公司