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Pin ball grid array encapsulation structure of wafer

An array packaging and chip technology, which is applied to electrical components, electric solid-state devices, circuits, etc., can solve the problems of easy falling off of solder balls, and achieve the effect of improving stability and reliability, and improving the effect of solder ball stress buffering.

Active Publication Date: 2009-04-22
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The main purpose of the present invention is to overcome the defects existing in the existing ball grid array packaging structure, and provide a new ball grid array packaging structure with pins on the chip. The technical problem to be solved is to make it possible to solve the problem of BGA packaging products There is no problem that the solder balls are easy to fall off due to the external pin lead frame, and it can improve the stability and reliability of wire bonding and ball planting, making it more suitable for practical use

Method used

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  • Pin ball grid array encapsulation structure of wafer
  • Pin ball grid array encapsulation structure of wafer
  • Pin ball grid array encapsulation structure of wafer

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0055] see figure 2 Shown is a schematic cross-sectional view of an on-chip ball grid array package structure according to the first embodiment of the present invention. A ball grid array package structure 200 according to the first specific embodiment of the present invention mainly includes a lead frame without external leads, a chip 220, a die bonding layer 230, a plurality of bonding wires 240, encapsulants 250 and a plurality of 260 solder balls. The pinless lead frame has a plurality of pins 210 , and the outer ends of the pins 210 are roughly aligned with the edge of the sealing body 250 , and can be slightly protruded or recessed. Usually, the pins 210 are made of metal, such as copper, iron or their alloys, which can be formed by stamping or etching. Each pin 210 has an upper surface 211 and a lower surface 212 . The lower surface 212 of each pin 210 defines a wire bonding area 213 and a ball receiving area 214 , which are respectively available for the connection...

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Abstract

The utility model relates to a packaging structure for the pin ball-lattice arrays on wafers, mainly comprising a non-external pin conductor frame, a wafer, an adhesive-wafer layer, a plurality of welding wires, a sealing adhesive body and a plurality of welding beads. The adhesive-wafer layer is formed between the active surface of the wafer and the upper surface of the pin of the non-external pin conductor frame; the welding wires are in electric connection with the wafer and the pins; the welding beads are arranged in the catching region of the lower surface of the pins; the sealing adhesive body is used to seal the upper surface of the pins, the adhesive-wafer layer and the welding wires, the lower surface except the region for arranging the welding beads, and the side faces between the lower surface and the upper surface of the pins; the sealing adhesive body is provided with a plurality of counterbores to make the exposed catching region relatively concave in a bottom surface of the sealing adhesive body. With the structure, the utility model solves the problem that the welding beads fall off easily, and improves the stability and reliability of solder sphere placement and wire bond.

Description

technical field [0001] The invention relates to a ball grid array packaging technology for a semiconductor chip without using a circuit board, in particular to a pin on a chip that can solve the problem that solder balls are easy to fall off, and can improve the stability and reliability of wire bonding and ball planting Type Ball Grid Array package structure (Ball Grid Array package with leads on chip). Background technique [0002] The conventional ball grid array (BGA) packaging structure uses a circuit board as a chip carrier, and the circuit board is provided with slots for the passage of bonding wires for bonding. Usually this ball grid array packaging structure can be called window type ball grid array (Window BGA), board chip type ball grid array (Chip-On-Board BGA) or chip on the substrate ball grid array (Chip-On-Board BGA) -Substrate BGA). [0003] see figure 1 Shown is a schematic cross-sectional view of a conventional ball grid array package structure. The c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/488
CPCH01L2224/4824H01L2224/48091H01L2224/48465H01L2224/73215H01L2224/32225
Inventor 林鸿村
Owner CHIPMOS TECH INC