Pin ball grid array encapsulation structure of wafer
An array packaging and chip technology, which is applied to electrical components, electric solid-state devices, circuits, etc., can solve the problems of easy falling off of solder balls, and achieve the effect of improving stability and reliability, and improving the effect of solder ball stress buffering.
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[0055] see figure 2 Shown is a schematic cross-sectional view of an on-chip ball grid array package structure according to the first embodiment of the present invention. A ball grid array package structure 200 according to the first specific embodiment of the present invention mainly includes a lead frame without external leads, a chip 220, a die bonding layer 230, a plurality of bonding wires 240, encapsulants 250 and a plurality of 260 solder balls. The pinless lead frame has a plurality of pins 210 , and the outer ends of the pins 210 are roughly aligned with the edge of the sealing body 250 , and can be slightly protruded or recessed. Usually, the pins 210 are made of metal, such as copper, iron or their alloys, which can be formed by stamping or etching. Each pin 210 has an upper surface 211 and a lower surface 212 . The lower surface 212 of each pin 210 defines a wire bonding area 213 and a ball receiving area 214 , which are respectively available for the connection...
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