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Method and system for reducing power consumption of storage unit

A technology of memory and power consumption, applied in static memory, digital memory information, information storage, etc., can solve the problem of waste of power consumption, and achieve the effect of reducing power consumption, reducing leakage current, and avoiding waste of power consumption

Inactive Publication Date: 2009-07-01
VIMICRO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the test control unit does not need to be flipped at all in the functional mode, this system clock control scheme is likely to cause waste of power consumption, which is also very unfavorable to the current trend of low power consumption and small area system design

Method used

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  • Method and system for reducing power consumption of storage unit
  • Method and system for reducing power consumption of storage unit
  • Method and system for reducing power consumption of storage unit

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Embodiment Construction

[0026] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0027] The basic idea of ​​the present invention is to extend the sampling time of the SRAM gating clock, use the extended gating clock to sample the memory enabling signal, and control the SRAM according to the sampling result.

[0028] After extending the sampling time of the SRAM gating clock, the gating clock can have enough time to sample the high level of the memory enable signal. Therefore, the real shutdown of the SRAM can be realized, the generation of leakage current can be reduced, and the power consumption of the memory can be reduced.

[0029] Regarding how to extend the sampling time of the SRAM gating clock specifically, there are many implementation methods. For example, see Figure 5 The schematic diagram of the system structure for r...

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Abstract

The present invention provides a method for reducing memory power consumption, the method comprising: extending the sampling time of a static memory (SRAM) gating clock, and controlling the SRAM by using the extended gating clock to sample a memory enable signal. In addition, the present invention also provides a system for reducing memory power consumption, which includes: SRAM, OR gate, AND gate and at least one delay unit. The invention can reduce the power consumption of the memory and adapt to the current system design trend of low power consumption and small area.

Description

technical field [0001] The invention relates to data storage control technology, in particular to a method and system for reducing memory power consumption. Background technique [0002] There are usually a large number of data processing units in any communication system, and each data processing unit often requires a corresponding data storage unit to store data. Static memory (SRAM) is an indispensable data storage unit in communication system design, and its power consumption is also the largest in the entire system power consumption, even exceeding 60%. Nowadays, with the continuous increase of system design scale and data processing volume, the demand for static memory is increasing, and at the same time, the power consumption brought by static memory is also increasing. Therefore, how to reduce the power consumption of the memory has become a hot topic for the current system design trend of low power consumption and small area. [0003] figure 1 Shown is a schemati...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413G11C29/00
Inventor 庞科
Owner VIMICRO CORP