Stack packaging structure

A technology of packaging structure and chip packaging structure, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems that affect the reliability of stacked packaging structure, reduce the yield of packaging process, and incomplete bonding, etc. Achieve the effects of preventing false soldering, improving yield and reducing area

Active Publication Date: 2009-08-05
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, because the space between the substrate 102 of the chip packaging structure 100 and the substrate 202 of the chip packaging structure 200 is still quite large, and the junction between the chip packaging structure 100 and the chip packaging structure 200 falls in the peripheral area, a cold will be formed. Welding (ColdJoint), resulting in incomplete joint problems
This will seriously affect the reliability of the stacked packaging structure, and greatly reduce the yield of the packaging process, resulting in a significant increase in cost

Method used

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Embodiment Construction

[0019] Relevant detailed description and technical contents of the present invention are as follows now in conjunction with the accompanying drawings:

[0020] Figure 4 to Figure 9B It is a process sectional view of a stacked packaging structure according to a preferred embodiment of the present invention, and please also refer to Figure 12A . When making the stacked package structure of the present invention, first make the chip package structure 324a, for example Figure 8 structure shown. When fabricating the chip package structure 324a, the substrate 300a or the substrate 300b is provided first, wherein the substrate 300a or the substrate 300b may be a printed circuit board (PCB). The substrate 300a has an opposite surface 326a and a surface 328a, and the substrate 300b has an opposite surface 326b and a surface 328b. It should be noted that when the substrate 300b is provided by the supplier, several electrical connection elements 312d have been provided on the surf...

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Abstract

A stacking type package structure at least comprises one substrate, at least one chip, a plurality of electrical connection elements and a seal gum body, wherein the substrate has a first surface and a second surface opposite to each other; the chip is arranged on and in electrical connection with the first surface of the substrate; the electrical connection elements are arranged around the first surface of the substrate with one electrical connection element higher than the chip; the seal gum body is coated on the first surface of the substrate, the chip and the electrical connection elements with one surface of the seal gum body exposed out of the top end of each electrical connection element.

Description

technical field [0001] The present invention relates to a system-in-package (System-In-Package; SIP) structure, in particular to a stacked (Stacked) package structure. Background technique [0002] The demand for low cost, small size and multi-function has become the main driving force for the development of the electronics industry. To achieve these goals, many advanced packaging technologies have been developed, such as flip chip, chip scale package (Chip Scale Package; CSP), wafer level packaging, and three-dimensional packaging (3DPackage) technologies. The three-dimensional packaging technology can integrate the chip, packaging and passive components into a package, and can become a solution for system packaging. The integration of the three-dimensional packaging technology can be side-by-side, stacked or a combination of the above two methods. Three-dimensional packaging has the advantages of small footprint, high performance and low cost [0003] Figure 1 to Figur...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L25/16H01L23/488H01L23/31
CPCH01L2224/48091H01L2924/19107H01L2224/48227H01L2924/19105H01L2924/30107H01L2924/19106H01L2224/32145H01L2224/73265H01L2924/00014H01L2924/00
Inventor 李龙吉
Owner ADVANCED SEMICON ENG INC
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