Memory cell test circuit for semiconductor memory device and its method

Abstract

A memory cell test circuit used in a semiconductor memory device having a plurality of memory banks connected to a plurality of global input / output lines, comprising: a plurality of memory bank switching units for controlling based on a test mode signal and a plurality of A clock signal transmits data output from a plurality of memory banks to a plurality of global input / output lines; a logical operation unit is used to perform a logical operation on data output to a plurality of global input / output lines and to output a result of the logical operation to a test global input / output line; and a switch unit coupled to the test global input / output line and the plurality of global input / output lines for selectively passing the test global input based on the test mode signal and the plurality of control clock signals / Output line data and global I / O line data.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly, to a circuit for testing memory cells included in the semiconductor memory device. Background technique [0002] Since a semiconductor memory device is highly integrated, the test time taken for testing a memory cell included in the semiconductor memory device is increased. Therefore, recently, a test circuit capable of testing a plurality of memory cells at a time has been developed. That is, the test circuit tests the plurality of memory cells by inputting the same logic data to the plurality of memory cells and detecting output logic values ​​generated by performing a logic operation to output values ​​of the plurality of memory cells. [0003] figure 1 A block diagram for testing a memory cell showing a conventional single data rate synchronous semiconductor memory (SDR SDRAM) device. It is assumed here that the traditional SDR SDRAM includes two banks. [00...

AI Technical Summary

Problems solved by technology

[0034] However, as mentioned above, each bank of conventional SDR SDRAM includes test global input / output lines and a logic operation unit, which increases the size of conventional SDR SDRAM

Moreover, if the above-mentioned test circuit is used for a double data rate (DDR) SDRAM or DD2 SDRAM, the size of the test circuit will be further increased

Images