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Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree

A calibration device, floating-point multiplication technology, applied in instruments, electrical digital data processing, digital data processing components, etc., can solve problems such as data calculation errors

Active Publication Date: 2009-10-28
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the multiplication only takes 106 bits, this error is masked in the multiplier, and if no processing is done in the multiplier, it will cause calculation errors for some data due to wrong carry

Method used

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  • Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree
  • Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree
  • Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree

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Embodiment Construction

[0043] In order to make the purpose, technical scheme and advantages of the present invention clearer, below in conjunction with accompanying drawing and embodiment, a kind of floating-point multiplication adder of the present invention and its multiplication Carry Save Adder (CSA) compression tree carry checking device For further details. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0044] In order to achieve the purpose of the present invention, as figure 1 As shown, the floating-point multiplier-adder of the present invention includes an inverter 6, a bit alignment shifter 7, the first multiplication carry-save adder (CSA) 1, the second 3: 2 carry-save adder (CSA) 2, A 161-bit adder 5, a normalization and rounding unit 8, and a carry-check arrangement for a multiplicative carry-save adder (CSA) compression tree in parallel with a second 3:2 carry-save adder (CSA) ...

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Abstract

The invention discloses a carry check device for a compressed tree of a multiplication carry-save adder (CSA) in a floating-point multiply-adder, which includes a carry judgment unit and a carry check unit, and the carry judgment unit is used for floating-point The two operands A and B of the multiplier adder are compressed by the first carry-reserving adder, and the data of the compressed carry part and the compressed sum part are used as input values ​​to determine whether the result of the addition is carry, and output the carry check digit according to the carry situation M; the carry check unit is used for the high 55 bits (bit) of the Cinvshift after the carry check bit M output by the carry judgment unit, the operand C, and the second 3:2 compressed carry reserve adder The highest bit of the carry compression result is carried out for carry correction, and the two sets of 55-bit values ​​are output to the upper 55 bits of the two sets of data of the 161-bit adder. It causes the Carry Save Adder (CSA) compressed result to be corrected so that the multiply adder calculation is correct.

Description

technical field [0001] The present invention relates to the technical field of microprocessors, in particular to a floating-point multiplication-add component design technology in a microprocessor, in particular to a floating-point multiplication-adder and its multiplication carry-save adder (CSA) compression tree Carry check device. Background technique [0002] In order to achieve high efficiency of floating-point calculations, both floating-point multiplication and addition in the microprocessor are implemented using a floating-point arithmetic unit-a floating-point multiply-adder (Floating-point Multiply-Add Fused Unit, FMAF). The instruction execution of the floating-point multiply-accumulator (FMAF) requires 3 operands A, B, and C to perform (A×B)+C operations. When the operand C in the multiply-add instruction is set to 0, the multiplication instruction is executed. , when the operand B is set to 1, the addition instruction is executed. [0003] The operand of the f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/57
Inventor 齐子初胡伟武
Owner LOONGSON TECH CORP