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Data processing system and high-definition TV including the data processing system

A data processing system and data width technology, applied in high-definition television systems, electronic digital data processing, processor architecture/configuration, etc., and can solve problems such as processing performance limitations and processing speed limitations

Active Publication Date: 2012-05-30
MARVELL ASIA PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The processing performance of the processing system 10 is limited by the capacity of the communication bus 24
In other words, the processing speed is limited by the speed and / or bandwidth of the communication bus 24

Method used

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  • Data processing system and high-definition TV including the data processing system
  • Data processing system and high-definition TV including the data processing system
  • Data processing system and high-definition TV including the data processing system

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Embodiment Construction

[0037] The following description is merely exemplary in nature and is in no way intended to limit the invention, its application or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the terms module, circuit, and / or device refer to an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that executes one or more software or firmware programs, combinational logic circuits, and / or other suitable components that provide the described functionality. As used herein, the phrase "at least one of A, B, and C" should be construed to mean a logical (A or B or C) using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the invention.

[0038] According to the present invention, a processing system includes a multi-ported data memory archi...

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Abstract

This invention disclose a processing system. A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses. A first one of the N hardware acceleration modules performs a first processing task on data and transmits thedata to the multiport memory module on a first one of the N data communication buses. A second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N data communication buses and performs a second processing task on the data. N is an integer greater than one.

Description

technical field [0001] This invention relates to data processing architectures, and more particularly to multi-ported data memory architectures for processing. Background technique [0002] Typically, data processing can be performed by dividing tasks between software and hardware. For example, some tasks are complex but not necessarily computationally intensive, so performing these tasks in software is sufficient. Other tasks are more computationally intensive, so it is more efficient to use hardware to perform them. Parallel processing can be used to speed up the processing of computationally intensive tasks. Parallel processing can be used for video processing, gaming, complex mathematical modeling, video conferencing, and / or other applications. [0003] Various central processing units (CPUs) and hardware acceleration modules are usually connected together through an on-chip bus. Data transfers between CPUs and / or hardware acceleration modules require high bandwidth....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F13/40G06T1/20H04N7/015
CPCG06F13/4027
Inventor 塞哈特·苏塔迪嘉
Owner MARVELL ASIA PTE LTD