Digital phase lock loop and its clock adjusting method

Abstract

A digital phase-lock loop and clock adjusting method, the locking module is used to detect how many delay units are required by delaying input clock for N clock periods; calculating module which is used to calculate the number of delay unit needed by input clock based on the input of system;The clock adjusting module which adjusts the input clock based on the calculating result of the calculating module; control module which is use to control the calculating module and clock adjusting module, the clock adjusting module includes the first delay chain and the second delay chain, the corresponding delay unit is selected based on the result of the calculating module, the clock adjusting module also includes switch control module which is used to choose one output of the first delay chain and the second delay chain as the output clock, the control module controls the first delay chain and the second delay chain based on the selection of the switch control module, and loads the calculation of the calculating module to unselected delay chain.

Description

technical field [0001] The invention relates to a digital phase-locked loop, in particular to a high-precision digital phase-locked loop. The invention also relates to a clock adjustment method of a digital phase-locked loop. Background technique [0002] In the digital TV set-top box, the digital decoding chip receives the digital code stream, divides the video and audio information in it, and sends them to corresponding modules for processing, and these modules work at a clock of, for example, 27MHz. The said digital code stream is sent to the digital decoding chip at an equivalent frequency of 27MHz (hereinafter referred to as the code stream frequency), but the code stream frequency cannot be completely consistent with the 27MHz frequency of the decoding chip itself (hereinafter referred to as the local clock), so that Cause overflow or underflow of the cache in the decoding chip. If the local clock is fast, the cache will be read empty, which is called underflow; if t...

AI Technical Summary

Problems solved by technology

The technical solution disclosed in this patent realizes dynamic compensation, but this solution has the following two defects: First, there is only one delay chain, which will cause a short clock overlap due to the reduction of delay units, which will cause serious glitches in the output clock ; Second, this scheme can only be used when the phase of the delay is a fixed value

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