Binary phase detector and clock data recovery device

Abstract

A binary phase detecting device (2) comprises a first decision feedback equaliser (DFE1) connected in parallel with a decision unit (DFE2), which can be devised as a second decision feedback equaliser. Respective outputs (Q) of the first decision feedback equaliser and the decision unit are input to a first (8) and to a second flip flop (9), respectively. Using this configuration, the proposed binary phase detecting device overcomes disadvantages of conventional binary phase detectors in the presence of highly distorted input signals, e.g. due to Polarisation Mode Dispersion (PMD), thus enabling high-performance clock data recovery (CDR) with increase dispersion tolerance.

Description

technical field [0001] The present invention relates to a binary phase detection device and a clock data recovery device comprising such a binary phase detection device. [0002] The invention also relates to a method of recovering clock data from a binary data signal. Background technique [0003] Apparatus for recovering clock data from a binary data signal generally includes a phase detector, such as a binary phase detector, that generates an output signal based on the phase difference of the clock and the non-regenerated data signal. A common example of a binary phase detector in the prior art is an Alexander or switched binary phase detector (binary PD) using a configuration of four easy decision flip-flops (DEF). When compared to commonly known linear phase detectors, binary phase detectors have the advantage that an output pulse of duration one bit period is delivered indicative of a leading or lagging clock phase. Such characteristics are especially beneficial for ...

AI Technical Summary

Problems solved by technology

However, as mentioned above, linear phase detectors (as opposed to digital or binary phase detectors) are generally less suitable for very high data rates

Images