Unlock instant, AI-driven research and patent intelligence for your innovation.

Double encapsulated semiconductor package and manufacturing method thereof

一种半导体、复合半导体的技术，应用在半导体/固态器件制造、半导体器件、半导体/固态器件零部件等方向

Inactive Publication Date: 2007-09-12
SAMSUNG ELECTRONICS CO LTD
View PDF0 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore additional costs are incurred in manufacturing a molding tool with runners corresponding to the positions of the second windows 37

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Double encapsulated semiconductor package and manufacturing method thereof
  • Double encapsulated semiconductor package and manufacturing method thereof
  • Double encapsulated semiconductor package and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0020] FIG. 2 is a plan view of a wiring substrate 130 of a double-sealed semiconductor chip according to a first embodiment of the present invention. FIG. 3 is a plan view showing a double hermetic semiconductor package 200 according to a first embodiment of the present invention. FIG. 4 is a sectional view along line IV-IV of FIG. 3 .

[0021] Referring to FIGS. 2 to 4, a semiconductor package 200 according to a first embodiment of the present invention is a BOC package in which a composite chip 110 is attached on a wiring substrate 130 in a face-down manner.

[0022] Composite chip 110 includes regular pads 114 which may be formed on both sides of active surface 112 and random pads 116 formed in an inner region of active surface 112 . The regular pads 114 are formed parallel to each other on both sides, and the random pads 116 are formed in two groups keeping a predetermined distance therebetween.

[0023] The wiring substrate 130 has a first surface 131 and a second surf...

example 2

[0044] Although in the first embodiment of the present invention, an example is shown in which the normal pads of the composite chip are formed in the edge pad type, the normal pads may also be formed in the center pad type as shown in FIG. 8 . The semiconductor package 300 according to the second embodiment of the present invention has the same structure as that of the first embodiment from the viewpoint that the composite chip 210 is attached face down to the first surface 231 of the wiring substrate 230 .

[0045] The regular pads 214 of the composite chip 210 are formed in the central area of ​​the active surface 212 , and the random pads 216 of the composite chip 210 are formed outside the central area of ​​the active surface 212 . The first window 235 and the second window 237 are formed so that the first window 235 and the second window 237 respectively correspond to the regular pad 214 and the random pad 216 of the composite chip 210 in the wiring substrate 230 . Also,...

example 3

[0048] Although an example of a semiconductor package equipped with a single composite chip has been shown in the first and second embodiments of the present invention, as shown in FIG. 325 and the semiconductor package 400 of the composite chip 310.

[0049] A semiconductor package 400 according to a third embodiment of the present invention is a multi-chip package having a first normal chip 321 and a composite chip 310 mounted horizontally on a first surface 331 of a wiring substrate 330, and having a A conventional chip 321 and a conventional chip 325 stacked vertically on the composite chip 310 .

[0050] The composite chip 310 and the first regular chip 321 are attached on the first surface 331 of the wiring substrate 330 with a predetermined distance therebetween. The first regular chip 321 may be an edge pad type semiconductor chip in which regular pads 323 are formed on both sides of the active surface 322 . Composite chip 310 may include regular pads 314 formed on b...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows are formed in the wiring substrate to respectively expose the normal and random pads, and to allow bonding wires to be connected to the normal and random pads with the wiring substrate. A first resin encapsulation portion is formed by a molding method in the first window and a second resin encapsulation portion is formed by a potting method in the second window.

Description

technical field [0001] The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having resin-sealed portions formed on both sides of a wiring substrate and a method of manufacturing the same. Background technique [0002] In the current electronic product market, demand for mobile electronic products is rapidly increasing, and miniaturization of components used in electronic products is important to meet the demand. A technology that reduces the size of a single semiconductor package mounted as a component, a system on chip (System on Chip, SOC) technology that enables multiple semiconductor chips to be formed into one chip, or a system in a package that integrates multiple single semiconductor chips into a package ( System in Package (SIP) technology is necessary to achieve this miniaturization. [0003] In the case of an SOC, the die pad arrangement may include a random arrangement type, in which the die pads are formed i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/28H01L23/488H01L23/498H01L21/50H01L21/56H01L21/60
CPCH01L23/3128H01L2924/15311H01L2924/01014H01L2924/01005H01L2224/32145H01L2924/01082H01L25/0657H01L2224/4824H01L2924/01015H01L2924/014H01L2224/48091H01L24/49H01L2224/06135H01L2224/49109H01L25/0652H01L2224/06136H01L2924/01006H01L2924/01033H01L2924/01028H01L24/48H01L2924/01079H01L2225/0651H01L2924/181H01L2924/00014H01L2924/15151H01L2924/00H01L2224/45099H01L2224/05599H01L2924/00012H01L23/28
Inventor 全柄硕金吉百李龙镇
Owner SAMSUNG ELECTRONICS CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com