Dynamic control of memory access speed

Abstract

A memory system is disclosed in which the access speed may be adjusted. The memory system may include memory and a memory controller. The memory controller may be configured to generate a plurality of control signals to access the memory, and adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.

Description

technical field [0001] The present invention relates generally to memory, and more particularly to dynamic control of memory access speed. Background technique [0002] Currently, memory is widely used in digital systems to store data required by various processing entities. Memory systems typically include a memory controller that manages access to memory. A typical memory usually has a matrix structure formed of rows and columns of memory cells, each of which is capable of storing data. A processing entity or other source can access the memory cells by providing the appropriate row and column addresses to the memory controller. Row and column addresses can be sent over the bus, with the row address occupying the lower order bits on the bus and the column address occupying the higher order bits on the bus. The row and column addresses are collectively referred to as "addresses" herein. [0003] A memory controller can be used to generate the appropriate control signals ...

AI Technical Summary

Problems solved by technology

These lower performance designs tend to extend battery life, but often cause one or more processing entities to wait to access memory

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