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Decoding method in an nrom flash memory array

A read operation, flash memory array technology, applied in information storage, static memory, read-only memory, etc., can solve the problem of the rise of the conduction voltage Vt

Active Publication Date: 2008-04-02
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the programmed cell 500, because the charge of the floating gate 506 increases, the turn-on voltage Vt of the cell also increases.

Method used

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  • Decoding method in an nrom flash memory array
  • Decoding method in an nrom flash memory array
  • Decoding method in an nrom flash memory array

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Embodiment Construction

[0049] Some terms used in the following description are only for the convenience of description, and do not constitute a limitation. Words such as "right", "left", "down", "up" are used in the drawings to denote directions. "Inwardly" and "outwardly" refer to directions toward or away from, respectively, the geometric center of an object or part thereof. These terms include the above-mentioned words and other terms derived from the above-mentioned words and similar related terms. In addition, "a" used in the claims and corresponding parts of the specification means "at least one".

[0050] As shown, wherein like numerals refer to like elements, FIGS. 3A-3E and 4A-4E illustrate a portion of a flash memory array 50 having a plurality of bit line transistors BLT1-BLT16 and a plurality of memory cells 61-76. 3A-3E and 4A-4E diagrammatically illustrate a preferred embodiment of the read pre-charge method of the present invention. FIG. 5 is a schematic diagram of the flash memory...

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Abstract

A read operation method is provided for a flash memory array having a plurality of memory cells, wordlines, even bitlines, odd bitlines and a plurality of bitline transistors. The method includes pre-charging the plurality of even bitlines to about Vcc / n and pre-charging the plurality of odd bitlines to ground. The current flowing to / from a first bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the first bit location in each of the memory cells. The method also includes pre-charging the plurality of odd bitlines to about Vcc / n and pre-charging the plurality of even bitlines to ground. The current flowing to / from a second bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the second bit location in each of the memory cells.

Description

technical field [0001] The invention relates to a decoding process of a flash memory, in particular to a method for precharging and decoding a memory array with a plurality of bit line transistors. Background technique [0002] Non-volatile memory (NVM) is a type of semiconductor memory in which a device containing NVM memory cells can continue to store data even after power is turned off. For a typical NVM, data can be programmed and read and / or erased. Programmed data can be stored for a long period of time before being erased. Flash memory (flash memory) is a special existing NVM memory, which is an electrically erasable programmable read-only memory (EEPROM). [0003] A typical flash memory stores information in an array of transistors often referred to as "cells," with each cell typically storing one bit of information. Flash memory is based on floating-gate avalanche-injected metal-oxide-semiconductor technology (FAMOS transistors). A FAMOS transistor is essentiall...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/24
CPCG11C8/10G11C17/12
Inventor 金钟五权彝振刘承杰
Owner MACRONIX INT CO LTD