Multi-load topology cabling architecture

Abstract

A multiple load topological wiring structure applies to wiring of multiple signal receiving ends for the same signal transmitting end on a printed circuit board. The signal transmitting end is connected to a first connection point via a main transmission line; the first connection point is connected to a second connection point and a first signal receiving end respectively via two branch transmission lines; the second connection point is connected to a second signal receiving end and a third signal receiving end respectively via two branch transmission lines; the distance between the second signal receiving end and the signal transmitting end is larger than the distance between the first and the third signal receiving ends and the signal transmitting end; a damping resistor is connected in series on the transmission line between the second connection point and the second signal receiving end.

Description

technical field [0001] The invention relates to a multi-load topological wiring structure, in particular to a multi-load topological wiring structure on a computer motherboard. Background technique [0002] On the printed circuit board, due to the limitation of the component placement space, there is a huge gap in the distribution of multiple loads on the same transmission end and the receiving end. Due to the unbalanced distribution of the distance between the loads on the computer motherboard, some high-frequency transients are caused. The signal is reflected from the farthest receiver to other closer receivers. At this time, a non-monotonic phenomenon (non-monotonic) will occur in the signal of the receiver closer to the load. This phenomenon will affect the signal integrity, resulting in timing and digital operations. mistake. [0003] For the line wiring of multiple loads, the existing method is to connect a resistor in series close to the signal transmission end to ma...

AI Technical Summary

Problems solved by technology

However, in the actual design, due to the limitation of the position of the chip at the receiving end, the lengths of each section of the transmission line are quite different. In Fig. 70 will reflect the high-frequency transient signal to the receiving end 60, 80, 90, and produce non-monotonic phenomenon at the receiving end 60, 80, 90, which affects the signal integrity and causes timing and digital operation errors

Please refer to Figure 2, which is the waveform diagram on the receiving end of the existing multi-load wiring architecture, in which the signal curves 66, 77, 88, and 99 correspond to the signal simulation curves of the receiving end 60, 70, 80, and 90, we can see The signal simulation curves 66, 88, 99 corresponding to the receiving ends 60, 80, 90 have serious non-monotonic phenomena during the rising period, resulting in timing and digital operation errors

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