Surge filter and clock data recovery circuit having the filter

Abstract

The invention provides a sudden wave filter, relating to a digital clock data resuming (CDR) circuit. The existing CDR circuit has the problem that sudden wave interruption is hard to eliminate. The sudden wave filter of the invention includes a first logic circuit used for receiving sampling latching data and filtering data and detecting whether the data corresponding to three neighboring phasesaccords with the combination of (0,1,0) or (1,0,1); if so, then data detecting signal is generated. The sudden wave filter of the invention includes a second logic circuit used for receiving the datadetecting signal transmitted by the first logic circuit and data jumping signal feed backed by the clock data resuming circuit and judging whether the data corresponding to three neighboring clock phases has a sudden wave based on the two signals. The invention also includes a third logic circuit which generates a corresponding filtering data and feeds the filtering data back to the first logic circuit according to the judging result of the second logic circuit. By adopting the filter of the invention, the sudden wave signal can be filtered before the sudden wave enters a CDR back-grade circuit, so as to reduce the error rate of the CDR circuit and improve the circuit reliability.

Description

technical field [0001] The invention belongs to the field of integrated circuit manufacturing and relates to a digital clock data recovery circuit, in particular to a filter for preventing surge interference and a clock data recovery circuit with the filter. Background technique [0002] The data recovery of the digital clock data recovery (CDR, Clock and Data Recovery) circuit mainly detects the data transition phase (data transition phase) through over-sampling, and selects the appropriate sampling phase (sampling phase) to sample and Data recovery. figure 1 It is an existing digital CDR circuit adopting an 8-fold oversampling rate, which limits jitter within two clock phases of each data transition edge. In the figure, φ 0 to φ 7 Corresponding to 8 oversampling phases respectively, two adjacent φ 0 There is one data between, and the jitter will only occur at the φ of the data transition edge 7 to φ 1 range, therefore, for a data, its transition may occur in the phas...

AI Technical Summary

Problems solved by technology

However, since this scheme is only for jitter interference (occurs only on the data edge), it is not suitable for surge interference (may occur anywhere in the data), therefore, a method that can effectively prevent the occurrence of surges in high-speed serial data communication is needed. Interfering CDR circuit

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