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An Interconnect Model for Heterogeneous Reconfigurable Processors

A heterogeneous, processing core technology, applied in the field of interconnected network models and interconnected models

Inactive Publication Date: 2011-12-07
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in the heterogeneous reconfigurable processor architecture, the data width and the number of input and output data of each reconfigurable processing core are different, so the data transmission interconnection network between these reconfigurable processing cores becomes a difficulty

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  • An Interconnect Model for Heterogeneous Reconfigurable Processors
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  • An Interconnect Model for Heterogeneous Reconfigurable Processors

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Embodiment Construction

[0022] The following is a further illustration through an example of the interconnection model:

[0023] The interconnection model proposed by the present invention is instantiated in a heterogeneous reconfigurable processor architecture to illustrate the scale of the interconnection model proposed by the present invention. The processor architecture contains four heterogeneous reconfigurable processing cores 101, wherein the maximum number of input data of the reconfigurable processing core A is 32, the number of output data is 8, and the data width is 16 bits; The maximum number of inputs for reconfigurable processing core B is 16, the number of outputs is 8, and the data width is 16 bits; the maximum number of inputs for reconfigurable processing core C is 32, the data bit width is 16 bits, and the output data The number is 16, and the data bit width is 8 bits; the input number of the reconfigurable processing core D is 1, the data bit width is 1 bit, and the number of outp...

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Abstract

The invention belongs to the technical field of integrated circuit design, and specifically relates to an interconnection model suitable for a heterogeneous reconfigurable processor, which is used for data transmission and exchange of each heterogeneous reconfigurable processing core in the processor. This model normalizes the output of all kinds of heterogeneous reconfigurable cores, and then provides the fastest and most flexible interconnection. Through certain control bits, the data output from a reconfigurable processing core can be Input to any reconfigurable processing core for processing within two clock cycles.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to an interconnection model, in particular to an interconnection model suitable for heterogeneous reconfigurable processors, which is used for the data of each heterogeneous reconfigurable processing core in the processor. transmission and exchange. Background technique [0002] At present, reconfigurable processors have gradually gained wider application and development because of their advantages in versatility, flexibility, and high performance. Among them, since the heterogeneous reconfigurable processor architecture contains multiple different processing cores, the specific operations of each processing core are also different. Therefore, its area, power consumption and pertinence in specific fields Outperforms isomorphic reconfigurable processors. However, in the heterogeneous reconfigurable processor architecture, the data width and the number ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 陆雯青赵爽陆超周晓方
Owner FUDAN UNIV
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