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Testing of an integrated circuit that contains secret information

A technology of integrated circuit and signal generation circuit, which is applied in the direction of measuring electricity, measuring electrical variables, digital circuit testing, etc., and can solve the problem that it is difficult to identify the input end and output end of the scan chain without systematic efforts

Inactive Publication Date: 2008-08-06
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

No systematic effort has been made to make it difficult to identify scan chain inputs and outputs

Method used

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  • Testing of an integrated circuit that contains secret information
  • Testing of an integrated circuit that contains secret information
  • Testing of an integrated circuit that contains secret information

Examples

Experimental program
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Embodiment Construction

[0024] FIG. 1 shows an integrated circuit 10 comprising functional circuits 12 a - c , scan chain 14 , test control circuit 16 and fuse element 18 . Test control circuit 16 has an input coupled to external test interface 17 and a control output coupled to scan chain 14 (connections not shown). Scan chain 14 has an input coupled to a test data input of external test interface 17 and an output coupled to a test data output of external test interface 17 . Fuse element 18 is coupled to test control circuit 16 and scan chain 14 . The scan chain 14 is coupled to the input and output of the functional logic functional circuits 12a-c. Although a single input and output line is shown between the functional circuits 12a-c and the scan chain 14, it should be understood that in practice many such lines may be provided in parallel.

[0025] It should be emphasized that the drawings are limited to explaining aspects of the use of fuse element 18 in an integrated circuit. Any number of fu...

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PUM

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Abstract

An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a to c). A scan chain modifying circuit (43, 47, 70a to c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a to c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and / or operation of functional circuits.

Description

technical field [0001] The present invention relates to the testing of integrated circuits, in particular integrated circuits containing secret information which must be protected from unauthorized access. Background technique [0002] Testability and security impose conflicting design requirements on integrated circuits. Testability requires that each circuit element should be coupled to a scan chain such that expected defects in the circuit elements are revealed in response to signals from the circuit elements that are captured in response to test stimulus signals from the scan chain. in the scan chain. Therefore, it is easy to test the integrated circuit by applying the test stimulus and removing the test response using the scan chain. Unfortunately, this also means that signals in circuit elements affected by secret information are easily accessed through scan chains. [0003] On the other hand, privacy can be achieved with a circuit configuration in which the circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317
CPCG01R31/31719G01R31/318541
Inventor 安德烈·K·纽兰桑迪普库马尔·戈埃尔埃里克·J·马里尼森休伯特斯·G·H·韦尔默朗亨得里克斯·P·E·瓦兰肯
Owner NXP BV
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