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System, equipment and method for switching command of memory and processor of interface connection

A technology of a memory system, a conversion method, applied in the direction of input/output to a record carrier, etc., capable of solving the problems of increasing processor size cost, expensive, small storage capacity, etc.

Inactive Publication Date: 2010-12-29
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] As such, the use of a DDR link to a processor may result in an increase in the size of the processor and the costs associated therewith, while the use of an XDR memory connected to a processor may be more expensive and have a smaller footprint than other memory options. storage

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  • System, equipment and method for switching command of memory and processor of interface connection
  • System, equipment and method for switching command of memory and processor of interface connection
  • System, equipment and method for switching command of memory and processor of interface connection

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Embodiment Construction

[0017] In general, the present invention provides improved methods, devices and systems for interfacing processors and memories. For example, the present invention provides a switch circuit (eg implemented as a switch chip) that connects a processor to a DDR memory (eg SDRAM) of a computer system. More particularly, a computer system may include an XDR interface, such as an extreme input / output (XIO) link, to connect the processor to the conversion circuit, and a DDR interface (eg, a DDR link) to connect the conversion circuit to the DDR memory. The conversion circuit includes hardware adapted to convert a memory system command in a first format issued by the processor (that is, a memory system command in the XDR command format) into a command in a second format that can be received and processed by the DDR memory (that is, memory system commands in DDR command format). By employing an XIO link at the processor, the methods, devices, and systems disclosed herein potentially r...

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PUM

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Abstract

A command translation method, apparatus and system are provided for interfacing a processor and a memory. The processor initiates a memory system command in an extreme data rate (XDR) command format which is automatically converted by the command translation method, apparatus and system into a memory system command in a double data rate (DDR) format for forwarding to the memory. Associated with converting the memory system command to the DDR command format is controlling timing of one or more signals presented to the memory interface, the one or more signals being associated with processing the memory system command in the DDR command format. The processor has associated therewith an XDR memory interface controller which adjusts one or more timing parameters of the memory system command in the XDR command format so that DDR timing requirements for the memory system command in the DDR command format are met.

Description

technical field [0001] The present invention relates generally to computer systems and, more particularly, to methods, apparatus and systems for interfacing a processor issuing memory system commands in a first command format to memory in a second command format. Background technique [0002] Computer systems typically include a main processor coupled to memory, such as dynamic random access memory (DRAM), through a memory controller. More particularly, a conventional computer system today may include a processor connected to double data rate (DDR) memory, such as synchronous dynamic random access memory (SDRAM), through a DDR memory interface, such as a DDR link. [0003] DDR memory is less expensive than other memories available today, such as extreme data rate (XDR) memory, and has a higher storage capacity than other memories. For example, XDR memory is limited in the amount of memory capacity it can support and is more expensive than DDR2 or DDR3 memory. However, DDR ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
Inventor M·D·贝洛斯J·D·艾里什D·A·诺加德T·奥兹古纳
Owner INT BUSINESS MASCH CORP