Two transistor static random access memory and its memory cell

Abstract

The invention discloses a double transistor type static random access memory and the memory cell. The memory cell includes: a first N-type switching element which has a control end connected to a wordline, furthermore, a first end of the first N-type switching element is connected to a first bit line; a second N-type switching element which has the control end connected to the word line, furthermore, a first end of the second N-type switching element is connected to a bit line with opposite phase; a first memory node, a first end of the first memory node is connected to the second end of thefirst N-type switching element; and a second memory node, a first end of the second memory node is connected to a second of the second N-type switching element. The memory can reduce the SRAM distribution area by more than 40% compared with the SRAM composed of 6T memory cell. The user needs no external data refresh circuit to update the SRAM data.

Description

technical field [0001] The present invention relates to a static random access memory (static random access memory, hereinafter referred to as SRAM), in particular to a memory cell structure of a two-transistor type static random access memory. Background technique [0002] As we all know, random access memory (RAM for short) can be divided into dynamic random access memory (DRAM for short) and static random access memory (SRAM). As long as the SRAM is powered, the stored data will not disappear; on the contrary, the data stored in the DRAM must be periodically refreshed, otherwise the data will disappear. Furthermore, under the same operating frequency, due to the symmetrical circuit structure of the SRAM, the data in each memory cell of the SRAM is accessed faster than the data in the memory cells of the DRAM. Therefore, although the production cost of the SRAM is relatively high, the fast access buffer memory (cache) in the computer must be realized by using the SRAM. A...

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Problems solved by technology

However, the sense amplifier of the SRAM memory cell is realized by using single-ended sensing technology, and the wiring of the word line and the bit line of the SRAM memory cell is not compatible with the wiring of the word line and the bit line of the known SRAM memory cell.

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