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Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions

A technology of voltage control delay and multiplexer, applied in automatic control of power, electrical components, etc., can solve problems such as unexplainable mismatch, unacceptable static error and mismatch

Active Publication Date: 2008-10-01
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Although the embodiment shown in FIG. 1 is acceptable in some cases, it may cause a large static error (static error) in the feedback signal (and the entire delay-locked loop) between the phases of the clock signal.
Also, since this embodiment uses separate multiplexers / phase interpolators in the feedback path and the output clock signal, it may not account for the mismatch between the two elements
This static error and mismatch may not be acceptable for many applications, especially as the clock speeds of computers and other digital systems increase

Method used

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  • Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions
  • Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions
  • Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions

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Embodiment Construction

[0034] Referring now to FIG. 2 , there is shown a block diagram of one embodiment of a delay locked loop integrating multiplexer and phase interpolation functions into each element of the voltage controlled delay line (VCDL). In the illustrated embodiment, a delay locked loop (DLL) 100 includes a phase detector 102 coupled to receive a reference clock signal. A voltage controlled delay line (VCDL) 120 is also coupled to receive the reference clock signal. In addition to receiving the reference clock signal, phase detector 102 is also coupled to receive a feedback signal from voltage-controlled delay line 120 . Phase detector 102 is configured to perform a phase comparison between the reference clock signal and the feedback clock signal. The result of this phase comparison, an error signal, is delivered as output by phase detector 102 . It should be noted that in some embodiments, the reference clock signal and the feedback signal may be differential signals, while in other e...

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Abstract

A voltage controlled delay line (VCDL). The VCDL (120) includes one or more cells (125). Each of the one or more cells includes two or more inputs (Va, VaX, Vb, VbX) and an output (Vout, VoutX). Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).

Description

technical field [0001] The present invention relates to electronic circuits, and more particularly to delay locked loops (DLLs). Background technique [0002] A delay locked loop (DLL) is a circuit commonly used in computers and other digital systems. Delay locked loops can be used to provide arbitrary delays that are compensated for process, voltage, and temperature (PVT) variations. [0003] FIG. 1 shows an embodiment of a typical delay-locked loop. The delay locked loop includes a phase detector coupled to receive a reference clock and configured for phase comparison between the reference clock and a feedback signal. The output of the phase detector is received by a digital filter which then filters the digital signal and sends it to an up / down counter. The filtered signal received by the up / down counter represents the phase relationship between the reference clock signal and the feedback signal (wherein the purpose of the feedback loop is to align the falling edge of ...

Claims

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Application Information

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IPC IPC(8): H03L7/081
CPCH03L7/0812H03L7/0816H03L7/081
Inventor R·库马尔A·达加S·塞西
Owner ADVANCED MICRO DEVICES INC