Self-aligning shallow groove isolation structure, memory unit and method for forming the same

Abstract

The invention relates to a method for forming a self-aligning shallow groove isolation structure, which comprises the following steps: a side wall is added into a self-aligning shallow groove isolation structure technology for oxidation so as to form a filed oxide layer; then, grooves are formed at an isolation area and are filled by a liner oxide layer and a third insulated layer. By adding the side wall into the self-aligning shallow groove isolation structure technology for oxidation and forming the field oxide layer, a sharp angle formed at the contact place of the self-aligning shallow groove isolation structure and a grid medium layer is avoided. Correspondingly, the invention provides a self-aligning shallow groove isolation structure. The invention also provides a memory unit and a formation method thereof for preventing the forming of a sharp angle at the contact place between the self-aligning shallow groove isolation structure of the areas of the memory unit and peripheral circuits, and the grid medium layer.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a self-aligned shallow trench isolation structure, a memory unit and a forming method thereof. Background technique [0002] With the advancement of the semiconductor industry, integrated circuits are developing towards smaller sizes and faster computing speeds. When the size of integrated circuits is becoming smaller and smaller, how to effectively isolate components is the key to the development of integrated circuits. The purpose of the device isolation structure is to isolate the adjacent device region and prevent carriers from penetrating into the adjacent device from the substrate. [0003] Among various device isolation technologies, the local oxidation of silicon method (LOCOS) and the shallow trench isolation region process are the two most commonly used technologies, especially the latter, because of its small isolation area and the advantages of maintaining sub...

AI Technical Summary

Problems solved by technology

Since the formation of the trench and the formation of the gate dielectric layer will generate stress in the semiconductor substrate, the stress will be concentrated at the sharp corner 114 where the self-aligned shallow trench isolation structure 112 contacts the gate dielectric layer 102, resulting in leakage current , thus affecting the reliability of the device

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