Backing store buffer for the register save engine of a stacked register file

Abstract

A Backing Store Buffer is interposed between a Physical Register File and the Backing Store in a stacked register file architecture. A Register Save Engine temporarily stores data from registers in the Physical Register File allocated to inactive procedures on-chip, freeing the registers to be re-allocated to new procedures. When the a procedures complete and returns control to a prior, inactive procedure, the Register Store Engine retrieves data associated with the inactive procedure from the Backing Store Buffer to registers in the Physical Register File, and the registers are re-allocated to the inactive procedure. The Register Save Engine saves data from the Backing Store Buffer to to the Backing Store, incurring the significant performance degradation and power consumption required for off-chip RAM access, only when the Backing Store Buffer is full and more data must be saved from the Physical Register File.

Description

technical field [0001] The present invention relates generally to the field of processors, and more particularly to a backing store buffer for a register preservation engine in a stacked register file architecture. Background technique [0002] RISC processors are characterized by relatively small instruction sets, where each instruction performs a single instruction, eg, arithmetic, logical, or load / store operations. Arithmetic and logic instructions take their operands from and write their results to one or more general purpose registers (GPRs). GPR is an architectural register. That is, it includes discrete memory locations that are explicitly identified in the instruction set architecture and are directly addressed by instructions. [0003] GPRs are typically implemented in hardware as an array of high-speed, multi-ported registers, each register having a word width defined by the instruction set (eg, 32 or 64 bits). This array of physical registers is called the phys...

AI Technical Summary

Problems solved by technology

Therefore, increasing the size of the physical register file 1 incurs substantial area and complexity costs, as well as lower utilization of expensive hardware

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