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Varying mesa dimensions in high cell density trench MOSFET

A mesa and size technology, applied in the field of power MOSFET transistors, can solve problems such as large cell size

Inactive Publication Date: 2011-11-16
FAIRCHILD SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, many techniques to reduce this resistance result in larger cell sizes

Method used

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  • Varying mesa dimensions in high cell density trench MOSFET
  • Varying mesa dimensions in high cell density trench MOSFET
  • Varying mesa dimensions in high cell density trench MOSFET

Examples

Experimental program
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Embodiment Construction

[0022] figure 1 is a side view of a transistor cell with heavy body contact etch that may be included by embodiments of the present invention. The device includes a body or bulk region 110 , a drain region 120 , and a source region 130 .

[0023] Generally, when figure 1 When the transistor shown is on and conducting, it sources current through the inductor. When the transistor is off, the energy stored in the inductor produces a current through the device (shown here as I 0 ). This current causes an avalanche breakdown in the body diode. In an embodiment of the invention, the breakdown is non-destructive, and the transistor is designed to handle the current.

[0024] However, if the latch-base resistance becomes too large, the sink-source diode can become forward biased and start conducting significant current. The diode acts as the emitter of the bipolar transistor. The current generated due to this secondary bipolar effect is uncontrollable and can become large enoug...

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PUM

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Abstract

Circuits, methods, and apparatus for power MOSFETs having a high cell density for a high current carrying capability while maintaining a low pinched-base resistance. One device employs a number of transistor cells having varying mesa (regions between trench gates) sizes. A heavy body etch is utilized in larger cells to reduce the pinched-base resistance. This etch removes silicon in the mesa region, which is then replaced with lower-impedance aluminum. A number of smaller cells that do not receive this etch are used to increase device current capacity. Avalanche current is directed to the larger, lower pinched base cells by ensuring these cells have a lower BVDSS breakdown voltage. The large cell BVDSS can be varied by adjusting the critical dimension or width of the trench gates on either side of the wider mesas, or by adjusting the depth of the heavy body etch.

Description

technical field [0001] The present invention relates generally to power MOSFET transistors, and more particularly, to power MOSFET transistors having a variety of mesa sizes. Background technique [0002] The use of power MOSFETs is rapidly becoming common, and its ubiquity is sure to spread widely over the next few years as it is required in more and more applications. But the demands of these applications place a burden on the performance of these devices. Accordingly, there is a need for power MOSFET devices with improved performance. [0003] During normal operation, when conducting, the power MOSFET pulls current through the inductor. When the power MOSFET is turned off, the inductor maintains the stored energy. This stored energy produces a current through the inductor that decreases over time as a function of the inductor's quality factor, or "Q." When the device enters avalanche breakdown mode, current is dissipated in the power MOSFET. [0004] Avalanche curren...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/76
CPCH01L29/42372H01L29/7808H01L29/66727H01L29/66348H01L29/4236H01L29/7397H01L29/66734H01L29/66325H01L29/7813H01L21/18
Inventor 王琦戈登·乔治·西姆
Owner FAIRCHILD SEMICON CORP