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Multi-chip stacking construction having metal spacer

A stacked structure, multi-chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems that the overall grain area cannot be reduced and is not ideal

Inactive Publication Date: 2009-03-18
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The bead 124 does not provide the function of a pad, so that the overall die area cannot be reduced
[0005] The above-mentioned prior art still has unsatisfactory parts in actual use, so there is still room for improvement

Method used

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  • Multi-chip stacking construction having metal spacer
  • Multi-chip stacking construction having metal spacer
  • Multi-chip stacking construction having metal spacer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0050] The first chip 200a is fixed to the substrate 30 through the adhesive layer 230, and the active surface of the first chip 200a is provided with a plurality of first metal pads 240 and a plurality of second metal pads 250, wherein the adhesive layer 230 can be The present invention is not limited by pre-attaching on the substrate 30 or attaching the adhesive layer 230 on the back surface of the first chip 200a first. In addition, the purpose of the adhesive layer 230 of the present invention is to form a bond with the substrate 30 or the first chip 200a. Therefore, as long as it is an adhesive material with this function, it is an embodiment of the present invention, such as: adhesive tape or B-Stage materials, etc.; at the same time, the purpose of the substrate 30 of the present invention is to provide a bearing. Therefore, as long as it is a material with this function, it is an embodiment of the present invention, such as a circuit board or a BGA circuit board material. ...

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PUM

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Abstract

A package structure stacked with a plurality of chips comprises a base plate, a first chip and a second chip, wherein the base plate is provided with a plurality of metal contacts which are mutually connected, the first surface of the first chip is fixed on the base plate through an adhesion coating, and the second surface thereof is provided with a plurality of first metal bonding pads and a plurality of second metal bonding pads, and a plurality of metal protrusions are formed on the second metal bonding pads of the first chip. The first surface of the second chip is fixed with the metal protrusions through an adhesive coating, and a plurality of metal pads are arranged on the second surface thereof, and a plurality of metal wires are used to electrically connect the first metal bonding pads on the first chip and the first metal pads on the second chip with the metal contacts on the base plate, wherein the height of the metal protrusions is larger than the largest height of the bank of the metal wires.

Description

Technical field [0001] The invention relates to an integrated circuit packaging structure and a packaging method thereof, and more particularly to a packaging structure that uses metal protrusions on a chip as a support and heat dissipation in a multi-chip stack structure. Background technique [0002] In recent years, three-dimensional (Three Dimension; 3D) packaging has been carried out in the back-end manufacturing process of semiconductors in order to use the least area to achieve higher density or memory capacity. In order to achieve this goal, a chip stacked method has been developed to achieve three-dimensional (3D) packaging. [0003] In the known technology, for example, US Patent No. 6,335,562 discloses a structure 300 that uses a metal frame 350 and a resin layer 340 to form a multi-chip stack, such as figure 1 Shown. Obviously, in figure 1 In order to prevent the metal wires 360 of the lower chip 310 from contacting the back of the upper stacked chip 320, the metal ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L25/065H01L23/488H01L23/31
CPCH01L2924/0002H01L2224/83136H01L2224/48091H01L2224/48471H01L2224/73265H01L2224/32145H01L2224/4813H01L2224/05554H01L2224/32245H01L2924/181H01L2924/00014H01L2924/00012
Inventor 林鸿村吴政庭
Owner CHIPMOS TECH INC
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