Method and apparatus for generating clock signals for quadrature sampling

Abstract

The present invention provides a quadrature-sampling clock signals generation method and apparatus for use in a receiver. The apparatus firstly obtains an initial clock signal whose frequency is lower than twice of the carrier frequency of an input signal, then divides the frequency of the initial clock signal by two to obtain two quadrature intermediate clock signals, and finally divides the frequency of the two intermediate clock signals respectively to output two quadrature sampling clock signals. With the clock signal generation method and apparatus of the present invention, it is possible to operate a VCO at a relative low frequency, which will not only reduce the cost of the VCO, but also decrease the power consumption thereof.

Description

technical field [0001] The present invention relates to a receiver used in the field of wireless communication, and more particularly, to a method and device for generating a clock signal used in a quadrature sampling receiver. Background technique [0002] In conventional wireless communication receivers, before converting the RF signals received from the antenna into digital signals, they usually undergo a series of processing to advance to baseband or low-IF signals. In addition, the received RF analog signal is usually passed through a series of filters to filter out-of-band interference and suppress noise. This receiver configuration has good performance and simple requirements for each functional block due to the filtering of interference in a stage-by-stage manner during signal processing. At the same time, however, such receivers entail high costs due to the low integration level of the components. [0003] Recently, another receiver configuration has attracted con...

AI Technical Summary

Problems solved by technology

However, a VCO operating at such a high frequency is expensive and power hungry, so it is not economical to use such a VCO for a receiver

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