Inter-connecting structure for semiconductor package and method of the same

Abstract

An interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers. The invention may be applied in places requiring high efficient encapsulation.

Description

technical field [0001] The invention relates to a semiconductor crystal grain packaging structure, in particular to an interconnection structure used in a semiconductor grain packaging structure and a forming method thereof. Background technique [0002] The functions of the chip package include power distribution, signal distribution, heat dissipation, protection and support, etc. As semiconductors become more complex, conventional packaging technologies such as lead frame packages, flex packages, and rigid packages are no longer sufficient to produce high The demand for small dies of density components. In general, array packaging technologies such as Ball Grid Array (BGA) provide an interconnect structure with a higher surface density than the package. A typical ball gate array package includes a convoluted signal path, resulting in high impedance and an inefficient thermal path, resulting in poor thermal performance. As the density of packages increases, it becomes mo...

AI Technical Summary

Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide a semiconductor element packaging structure to solve the problem of low reliability during thermal cycle and operation

Images