Loading method of programmable logic device, processor and apparatus

Abstract

The invention discloses a loading method of programmable logic device, processor and apparatus, belonging to the technical field of network communication. The loading method of the programmable logic device is suitable for the apparatus with multiple processors, wherein one processor is corresponding to at least one programmable logic device, the method comprises that a preprocessor in multiple processors receives the loading information loaded with the programmable logic device; the loaded programmable logic devices are programmable logic devices corresponding to other processors except the preprocessor in the multiple processors, the preprocessor can perform the loading operation for the loaded programmable logic device according to the received loading information. The preprocessor canperform the loading operation for the loaded programmable logic device again after judging the loading failed according to the state indication signal outputted by the loaded programmable logic device. The maintenability and the reliability of the apparatus having multiple processors can be ensured.

Description

technical field [0001] The invention relates to the technical field of network communication, in particular to a loading method of a programmable logic device, a processor and a device with multiple processors. Background technique [0002] CPLD / EPLD (Complex Programmable Logic Device / Erasable Programmablelogic Device, Complex Programmable Logic Device / Erasable Programmable Logic Device) has a very wide range of applications. With the increase of the scale of CPLD / EPLD and the increase of internal integrated functions, devices using CPLD / EPLD, such as products or equipment, require more and more upgrades for CPLD / EPLD to eliminate early design defects or achieve more features. [0003] At present, there are two main methods for loading and upgrading CPLD / EPLD: [0004] Method 1: Load and upgrade through the JTAG (Joint Test Action Group Standard Test Access Port and Boundary-Scan Architecture, the boundary-scan test interface of the Joint Test Action Group) cable, as attach...

AI Technical Summary

Problems solved by technology

The failure of CPLD / EPLD online loading and upgrading will make the processor unable to obtain data from the program memory, and eventually cause the processor to fail to start normally

[0012] To sum up, the existing loading and upgrading methods either have the problem of poor device maintainability due to the lack of support for online loading and upgrading, or the problem of poor device reliability due to the failure of the processor to start normally

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