Method and apparatus for conditional broadcast of barrier operations

Abstract

A weakly-ordered processing system implements an execution synchronization bus transaction, or ''memory barrier'' bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may ''opt out'' of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.

Description

technical field [0001] The present invention relates generally to the field of computers and, in particular, to a method and apparatus for conditionally broadcasting memory barrier bus operations. Background technique [0002] Computers and other electronic systems and devices perform computing tasks in many applications. These systems and devices are usually more and more integrated by integrating multiple independent, specific function circuits or modules (such as processors, mathematical coprocessors, video and graphics engines, DMA controllers, GPS receivers, dedicated compression or encryption circuits, etc.) Incorporate more and more functionality beyond direct computation. High bandwidth data transfer between such devices and memory, as well as between the devices themselves, is critical to achieving the required levels of performance. Data communication buses are well-known structures that provide shared communication links between devices or modules in a processin...

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Problems solved by technology

In this way, memory barriers are propagated only when it is necessary to enforce bus transaction ordering

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