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Integrated circuit die structure and manufacture method thereof

A technology of integrated circuits and manufacturing methods, applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as difficulty, removal of residues, cell failure, etc.

Active Publication Date: 2011-08-03
HEJIAN TECH SUZHOU
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Currently, in the semiconductor manufacturing process, the etching of flash memory and non-volatile memory (NVM) cells produces polysilicon residues that have the potential to disable the above-mentioned cells during programming or erasing
Second, due to the process, it is difficult to remove the residue through the etching process

Method used

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  • Integrated circuit die structure and manufacture method thereof
  • Integrated circuit die structure and manufacture method thereof
  • Integrated circuit die structure and manufacture method thereof

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Embodiment Construction

[0024] The structure of an integrated circuit chip and its manufacturing method according to the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0025] Such as figure 1 As shown, during the manufacturing process of non-volatile memory or flash memory cells, if there is polysilicon residue between the source and the gate, it is easy to cause A-B or B-C failure, or leakage from the control gate to the source. Therefore, it needs to be improved.

[0026] Such as Figure 2-7 As shown, a method for manufacturing a wafer using a SiN pad in an oxidation process according to a preferred embodiment of the present invention is shown.

[0027] Such as figure 2 As shown, first a semiconductor substrate 11 is provided, on which a first polysilicon layer 13 and a second polysilicon layer 14 are deposited, and the thickness of the first polysilicon layer 13 is about Between, the thickness of the secon...

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Abstract

The invention provides an integrated circuit die structure and a manufacture method thereof. The manufacture method comprises the following steps: 1, depositing a first polysilicon layer and a second plysilicon layer on a substrate; 2, coating photo resist on the second polysilicon layer and / or the first polysilicon layer and etching the photo resist; 3, etching the first polysilicon layer and the second plysilicon layer, and removing the photo resist, partial first polysilicon layer and partial second polysilicon layer; 4, depositing an SiN pad, performing etching in a large area on the SiN pad, and making the pad minimum along polysilicon residue; and 5, oxidizing the plysilicon residue. The method has the advantage that the method increases a step of depositing the SiN pad to treat thepolysilicon residue, so the oxidized polysilicon residue cannot generate adverse influence on subsequent processes.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing technology, in particular to an integrated circuit chip structure and a manufacturing method thereof. Background technique [0002] Currently, in the semiconductor manufacturing process, the etching of flash memory and non-volatile memory (NVM) cells produces polysilicon residues, and the polysilicon residues have the potential to disable the above-mentioned cells during the programming or erasing process. Second, due to process reasons, it is difficult to remove the residue through the etching process. Contents of the invention [0003] In view of the above, it is an object of the present invention to provide a novel method for manufacturing integrated circuit wafers by using SiN pads followed by an oxidation step to oxidize the remaining polysilicon. [0004] The invention provides a method for manufacturing an integrated circuit chip structure, comprising the following st...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8247H01L27/115H10B69/00
Inventor 李秋德
Owner HEJIAN TECH SUZHOU