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Data reading circuit and method

A data reading and circuit technology, applied in the direction of digital memory information, information storage, static memory, etc., can solve the problems of increased burden, increased cost, and increased steps of analog delay

Active Publication Date: 2011-11-09
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the disadvantage of this type of circuit is that it requires additional test port 105, feedback port 107 and related wiring, resulting in an increase in cost and an increase in the steps of analog delay
It also increases the burden on the system

Method used

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  • Data reading circuit and method

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Embodiment Construction

[0030] Certain terms are used in the specification and the appended claims to refer to specific components. It should be understood by those of ordinary skill in the art that hardware manufacturers may refer to the same component by different nouns. This specification and the appended claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as a criterion for distinguishing. The reference to "comprising" throughout the specification and the appended claims is an open-ended term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting m...

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Abstract

The present invention provides a data reading circuit and a data reading method. The data reading circuit comprises a first buffer, a second buffer, a first selector, a second selector and a third buffer, wherein the first buffer is used for receiving a first data signal and sampling the first data signal according to a first edge of a first prearranged signal to generate a second data signal; the second buffer is used for sampling the second data signal according to a second edge of a second prearranged signal to generate a third data signal; the first selector is used for selecting and outputting the second data signal or the third data signal according to the phase difference between the first prearranged signal and the second prearranged signal so as to generate a fourth data signal; the second selector is used for selecting and outputting the fourth data signal or a fifth data signal according to a selecting signal to generate a sixth data signal; and the third buffer is used for sampling the sixth data signal according to the first edge of the second prearranged signal so as to generate the fifth data signal.

Description

technical field [0001] The present invention relates to a data reading circuit, and more particularly, to a data reading circuit that is corrected in real time according to the delay condition of a data reading frequency signal of a memory. Background technique [0002] In today's electronic devices, memories are often used to store various data, and such electronic devices usually use a data reading frequency signal to read data in the memory. However, with the advancement of technology, the configuration of circuits and various components in an electronic device becomes more and more complicated, and the data reading frequency signal may be delayed due to these wirings and components. For example, the data read frequency signal can cause errors in data read due to the delay caused by the bonding pads. If the memory is used in a mass-produced custom chip (Application-Specific Integrated Circuit; ASIC), this phenomenon will cause considerable trouble, because the characteri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10G11C7/22
Inventor 郭东政
Owner REALTEK SEMICON CORP
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