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Link reconfiguration method for PCIE interface and device thereof

An interface and link technology, which is applied in the field of link reorganization of PCIE interface, can solve the problems of unusable PCIE interface and low utilization rate of PCIE interface link, so as to reduce the probability of crash, improve utilization rate and ensure stability Effect

Inactive Publication Date: 2009-10-14
HUAWEI DIGITAL TECH (CHENGDU) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The inventor finds in the process of realizing the present invention, in this solution, although the damage of channel lane0 can not cause the scrapping of whole PCIE physical interface, if channel lane0 and channel lane15 are damaged simultaneously, even other channels (lane ) is still intact, the PCIE interface is still unusable, resulting in low utilization of the PCIE interface link

Method used

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  • Link reconfiguration method for PCIE interface and device thereof
  • Link reconfiguration method for PCIE interface and device thereof
  • Link reconfiguration method for PCIE interface and device thereof

Examples

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Embodiment 1

[0021] An embodiment of the present invention provides a method for link reorganization of a fast peripheral component interconnection PCIE interface, which will be described in detail below in conjunction with the accompanying drawings.

[0022] figure 1 For the method flowchart of this embodiment, the link reorganization method of the PCIE interface of this embodiment is applied to any device using the PCIE interface, wherein the PCIE interface device applying the method of the embodiment of the present invention is called the root complex as the master device , the slave device connected to the master device is called an endpoint device, such as figure 1 As shown, the method of the present embodiment mainly includes:

[0023] 101: When the PCIE interface link re-initializes the orientation, if the root complex finds that there is an endpoint device physically connected to it through the PCIE interface, and the electrical function of the link with the endpoint device is int...

Embodiment 2

[0030] An embodiment of the present invention also provides a method for link reorganization of a PCIE interface, which will be described in detail below in conjunction with the accompanying drawings.

[0031] figure 2 It is the method flowchart of this embodiment, and the method of this embodiment is applied to any device using the PCIE interface. In this embodiment, the PCIE interface is an X16 link as an example for illustration, that is to say, the X16 link has 16 link channels, such as figure 2 As shown, the method of the present embodiment includes:

[0032] 201: If a link channel is damaged in the PCIE interface link, re-initialize the orientation of the PCIE interface link;

[0033] Among them, the link initialization orientation is to configure and initialize the physical layer of the device, the port and the physical layer control of related links, so that the link can transmit normal data packet traffic.

[0034] Generally, when the PCIE interface is working, t...

Embodiment 3

[0059] An embodiment of the present invention also provides a link reorganization device for a PCIE interface, which will be described in detail below in conjunction with the accompanying drawings.

[0060] Figure 5 It is a block diagram of the apparatus of this embodiment, and the apparatus of this embodiment can be applied to any equipment using the PCIE interface, such as Figure 4 As shown, the link reorganization device of the PCIE interface of the present embodiment mainly includes:

[0061] Configuration unit 51, for when the PCIE interface link re-initializes the orientation, if there is an endpoint device that is physically connected through the PCIE interface, and when the electrical function of the link between the endpoint device is intact, it is connected to The available channel allocation channel number of the link of the endpoint device;

[0062] The processing unit 52 is configured to perform data transmission with the endpoint device by using the available...

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Abstract

The embodiment of the invention provides a link reconfiguration method for a PCIE interface and a device thereof. The link reconfiguration method comprises the following steps: when the orientation of the PCIE interface link of a root complex is initialized again, if an endpoint device connected with the root complex by the PCIE interface in a physical manner exists and the electrical function of the link between the endpoint device and the root complex is in good condition, a channel number is allotted to an available channel of the link connected with the endpoint device; and data transmission is conducted between the available channel with the channel number and the endpoint device. With the method and device, the self-adaptive reconfiguration of the PCIE interface link is utilized to the full extent and the provisions of a protocol are reasonably utilized to improve the utilization ratio of the link, thereby ensuring the stability and continuity of the data transmission of a system by the PCIE interface and avoiding the dead halt of the whole system.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a link reorganization method and device for a PCIE interface. Background technique [0002] PCIE (PCI-Express; Fast PCI (Peripheral Component Interconnect)) is a high-performance I / O bus that can be applied to mobile devices, desktop computers, workstations, servers, embedded computing and The bus that interconnects all peripheral I / O devices such as the communication platform. The most significant advantage of the PCIE bus is to increase the transmission bandwidth of the device. The current sending and receiving data rate of PCIE1.0 is 2.5Gbit / s. At the same time, each PCIE device has very few pins, which reduces the design of PCIE chips and boards. cost, and reduces the complexity of board design. [0003] A PCIE link (PCIE lane) is a physical connection between two devices. PCIE interconnection has a point-to-point link of X1, X2, X4, X8, X16 or X32. The channels in b...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/02H04L12/40
Inventor 苏毅
Owner HUAWEI DIGITAL TECH (CHENGDU) CO LTD
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