Chip design method for realizing Big Dipper satellite signal capture and sliding correlation

A signal capture and sliding related technology, applied in the field of satellite signal reception and capture, can solve the problems of a large number of RAMs, complex control circuits, and difficulty in sliding 1-bit data output, so as to avoid control operations and reduce control circuits.

Inactive Publication Date: 2009-10-28
北京华龙通科技有限公司 +1
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Due to the large amount of data that needs to be stored, if a RAM with a relatively wide bit width is used, it is difficult to realize the data output of 1 bit each time, which will make the control circuit very complicated
If a RAM with a narrow bit width is used, the amount of stored data is small. If the stored data remains unchanged, the number of RAMs used will be very large, which is not conducive to the layout and wiring of the back-end in chip design.

Method used

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  • Chip design method for realizing Big Dipper satellite signal capture and sliding correlation
  • Chip design method for realizing Big Dipper satellite signal capture and sliding correlation
  • Chip design method for realizing Big Dipper satellite signal capture and sliding correlation

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Embodiment Construction

[0016] Describe the implementation process of the present invention in detail below in conjunction with accompanying drawing:

[0017] Such as figure 1 As shown, the input PN code data first press figure 2 , 3 Write the input PN code and IQ data into RAM in the way shown, and follow the Figure 5 , 6 The output in the manner shown realizes data sliding.

[0018] Such as figure 2 , 3 , 4 shows how the PN code and IQ data are stored in the RAM. The IQ data is first written to the address 0 of the RAM, and then the data is written to the address 1 after writing the 488x8bit number. After that, 488x8bit is written each time. After the data is written to the next address, it has been written to address 127, and all IQ data is written. PN data writing is similar to IQ, each time 488bit data is written, then the next address data is written, and after the address is 63, PN data writing ends. All data is written as requested.

[0019] Such as Figure 5 As shown, every time...

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Abstract

The invention relates to a chip design method for realizing Big Dipper satellite signal capture and sliding correlation. An input control part stores input PN code data and IQ data in a local RAM through a hardware logic control circuit thereof, and then an output control part executes output control and DRAM rewrite control process. When realizing the sliding correlation, the rewrite function of DRAM and PN data slide so as to avoid too complicated control operation on the IQ data so that not only RAM with big bit width can be selected in the chip design to reduce the number of RAM, but also the scale of control circuits can be reduced, thus reducing great quantity of control circuits and meeting the requirement of the chip design by using RAM with bigger width.

Description

technical field [0001] The invention relates to the technical field of satellite signal reception and capture, in particular to a chip design method for realizing the sliding correlation of Beidou satellite signal capture. Background technique [0002] The general method of satellite signal acquisition is to slidingly correlate the local code with the received signal, obtain the correct code phase by judging the peak value, and then hand over the phase-adjusted local code to the following tracking and other modules. Among them, the implementation of the sliding correlation part is generally divided into two methods: real-time sliding correlation and sliding correlation after data storage. When implementing sliding correlation to capture Beidou signals, because the code speed of Beidou signals is faster, more methods are used for calculation after data storage . [0003] Due to the large amount of data to be stored, if a RAM with a relatively wide bit width is used, it is di...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01S1/02
Inventor 华中宋保军王祥峰马俊峰侯亚峰董飞任小雷
Owner 北京华龙通科技有限公司
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