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Data processing apparatus

A data processing device and memory technology, which is applied in data processing power supply, electrical digital data processing, memory address/allocation/relocation, etc., can solve the problems of not being used immediately, long time, and increased cost.

Inactive Publication Date: 2010-03-03
FUJITSU LTD
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  • Claims
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Problems solved by technology

Such a need leads to an increase in the size and cost of the data processing apparatus 100, 300 in the prior art example
In particular, since the storage capacity of the main memory 4 is larger than that of the register 1A or the cache memory, the time required for the main memory 4 to perform data saving processing is long
[0025] In addition, in the restart process after the power supply unit 6 is restored, the data processing apparatus 100, 300 of the prior art example cannot be used immediately because it takes a long time to configure and save data.

Method used

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no. 1 example

[0037] Figure 4 is a structural block diagram of the data processing apparatus 400 according to the first embodiment of the present invention. exist Figure 4 In , elements similar to those of the data processing apparatus 100, 300 described above are denoted by similar reference numerals and will not be described again.

[0038] The data processing apparatus 400 includes a CPU 10 , a register 10A installed in the CPU 10 , a cache memory 12 , a control section 3 , a main memory 14 , an HDD 5 , and a power supply section 16 .

[0039] MRG (Magnetoresistive Register) or MRAM (Magnetoresistive Random Access Memory) can be used as the register 10A. Since both MRG and MRAM are nonvolatile memories, data can be stored in the MRG or MRAM without being volatile (lost) even if an abnormality occurs in the power supply section 16 . Except for the register 10A, the CPU 10 itself can be configured the same as the CPU 1 of the data processing apparatus 100, 300 described above.

[004...

no. 2 example

[0088] Figure 7 is a block diagram showing the structure of the data processing apparatus 700 according to the second embodiment of the present invention. The data processing apparatus 700 of the second embodiment differs from the data processing apparatus 400 of the first embodiment in that the main memory 24 is a volatile memory connected to a backup power source (for example, a backup battery). Except for this difference, the configuration of the data processing device 700 is basically the same as that of the data processing device 400 . Therefore, in the following description of the second embodiment and Figure 7 Components similar to those in the data processing apparatus 400 of the first embodiment above are denoted by similar reference numerals, and will not be described in detail again.

[0089] In the data processing apparatus 700 according to the second embodiment, even when an abnormality occurs in the power supply section 16, data of the main memory 23 can be m...

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Abstract

A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging ofdata between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU fromaccessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.

Description

technical field [0001] Embodiments described in the present application relate to a data processing apparatus that does not need to save data even when an abnormality occurs in a power supply. Background technique [0002] figure 1 is a schematic diagram showing the structure of the data processing apparatus 100 according to an example of the prior art. A data processing apparatus 100 of a prior art example includes a CPU (Central Processing Unit) 1 , a cache memory 2 , a control section 3 , a main memory 4 , an HDD (Hard Disk Drive) 5 , and a power supply section 6 . The cache memory 2, the control section 3, the main memory 4, and the HDD 5 are connected by a bus. [0003] The CPU 1 reads, for example, a program or data stored in the HDD 5, executes calculation processing according to the program, and outputs a calculation result. The CPU 1 includes a register 1A that temporarily stores data such as address data used when reading from a calculation result or the main me...

Claims

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Application Information

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IPC IPC(8): G06F12/08
CPCG06F12/08G06F11/30G06F1/30G06F2212/222G06F12/0802G06F2212/2024Y02D10/00
Inventor 宫崎贞夫石桥修中野力藏目崎义宪
Owner FUJITSU LTD
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