Port bandwidth guaranteed packet switching chip and implementation method thereof

Abstract

The invention discloses a port bandwidth guaranteed packet switching chip and a method for implementing port bandwidth guarantee in the packet switching chip. A mechanism similar to a time division multiplexing in a circuit switching system is used for assigning a corresponding number of time division slices according to sizes of different port bandwidths, which causes that the bandwidth can be strictly guaranteed once a plurality of ports at different rates start data burst transmission, thereby preventing complicated dispatching mechanism and greatly reducing design difficulty. Meanwhile, configuration of the time division slices can be changed accordingly by software configuration according to combined change of port rate and port number, which greatly improves flexibility. In addition,the design method can lower requirement for sending cached data to a port, further saving space of the chip.

Description

Technical field [0001] The present invention relates to the field of data communication, in particular to a technology for realizing port bandwidth guarantee in a packet switching chip. Background technique [0002] The ports in the packet switching chip, such as the Ethernet port, have such characteristics. Once the message header starts to be sent, the internal scheduling unit needs to continuously schedule the remaining part of the message at the same rate as the port and transmit it to this port. Once the internal scheduling rate cannot keep up, an underflow error occurs on the port, causing a complete message to be divided into two or more messages, which are discarded when the peer device receives it. [0003] Furthermore, when there are multiple ports with different rates, and there are multiple combinations of these ports with different rates, for example, for a packet switching chip with a switching capacity of 88Gbps, any combination of ports that can accommodate the swit...

AI Technical Summary

Problems solved by technology

[0004] In the traditional packet switching chip, one way is to realize the bandwidth guarantee of the port by designing a specific MMU (memory management unit), which is very complicated to implement, and can only be designed according to a specific port combination. If the port combination mode changes, another MMU needs to be designed, or a chip needs to be redesigned, such as the design method of the patent US 6335932B2

[0005] Another method is that each port corresponds to a scheduler to ensure the bandwidth of the port. This method will cause the area of ​​the chip to increase linearly with the increase of the number of ports, resulting in a large increase in chip area and chip cost.

[0006] The patent US 6732199 B1 also uses a mechanism similar to time division multiplexing, but on the one hand, this patent is based on the scheduling of the entire data packet, and the granularity is too large to be suitable for port-level scheduling. On the other hand, the more important thing is that the scheduler needs a High-speed search logic to update the content and status in the Calendar in a timely manner. In addition, for different queues or ports, additional registers are required to configure the sequence and number of time slots occupied by the queues or ports.

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